Three Dimensional Simulation of Filling Process for Stacked-Chip Scale Packages

  • Mior Firdaus Mior Abd MajidEmail author
  • Mohamad Sabri Mohamad Sidik
  • Muhamad Husaini Abu Bakar
  • Khairul Shahril Shafee
  • Zainal Nazri Mohd Yusuf
  • Mohamad Shukri Mohd Zain
  • Mohd. Zulkifly Abdullah
Part of the Advanced Structured Materials book series (STRUCTMAT, volume 102)


Encapsulation is one of the key processes in electronic packaging in order to protect the integrated circuit chips from environmental and mechanical damages. The most obvious choice for the encapsulation process is transfer moulding due to its capability to mould small parts with complex features. An electronic package that employs transfer moulding is Stacked-Chip Scale Package (S-CSP). However, a computer simulation is one of the tools that could be used to simulate and predict the mould process. It is highly desirable in order to avoid the typical time-consuming procedure of mould design and process optimization by trial and error. In this paper, a fully three-dimensional analysis to predict the transfer moulding process of S-CSP encapsulation using a finite volume method (FVM) based software, FLUENT is presented. The proposed FVM simulation model is built and meshed using GAMBIT. Some simplification is done for the simulation model due to time consumption and the complicated geometry of the actual S-CSP model. In the analysis, the volume of fluid (VOF) technique was used to track the flow front of the encapsulation. The viscosity versus shear rate is plotted and the void formation problem is also discussed. The numerical results are compared with the previous experimental results and are in good agreement.


Stacked-Chip Scale Package (S-CSP) Finite volume method (FVM) Volume of fluid (VOF) Front tracking Void 


  1. 1.
    Tummala, R.R.: Fundamentals of Microsystems Packaging, pp. 44–79. McGraw Hill, Singapore (2001)Google Scholar
  2. 2.
    Manzione, L.T.: Plastic Packaging of Microelectronic Device, pp. 1–35. Van Nostrand Reinhold, New York (1990)Google Scholar
  3. 3.
    Liang, C.W., Kulakarni, V.M., Aswatha Narayana, P.A., Seetharamu, K.N.: Parametric studies in transfer molding for Newtonian flids. J. Phys. Sci. 16(2), 103–114 (2005)Google Scholar
  4. 4.
    Kulkarni, V.M., Seetharamu, K.N., Azid, I.A., Aswatha Narayana, P.A., Quadir, G.A.: Numerical simulation of underfill encapsulation process based on charecteristic split method. Int. J. Numer. Meth. Engng. 66, 1658–1671 (2006)CrossRefGoogle Scholar
  5. 5.
    Kada, M., Smith, L.: Advancements in Stacked Chip Scale Packaging (S-CSP) provides system-in-a-package functionality for wireless and handheld applications. Future Fab. Intl. 9, 246–251 (2000)Google Scholar
  6. 6.
    Sze, M.W.H., Papageorge, M.: Encapsulation selection, characterization and reliability for fine pitch BGA (fpBGA). In: 4th Annual Flip Chip, BGA, Chip Scale Packaging ’98, April 28–29, 1998, pp. 1–7 (1998)Google Scholar
  7. 7.
    Pei, C.C., Hwang, S.J.: Three-dimensional paddle shift modelling for IC packaging. Trans. ASME J. Electron. Packag. 127, 324–334 (2005)CrossRefGoogle Scholar
  8. 8.
    Nguyen, L., Quentin, C., Lee, W., Bayyuk, S., Bidstrup-Allen, S. A. and Wang, S.T.: Computational modeling and validation of the encapsulation of plastic packages by transfer molding. Trans. ASME J. Electron. Packag. 122, 138–146 (2000)CrossRefGoogle Scholar
  9. 9.
    Chang, R.-Y., Yang, W.-S., Chen, E., Lin, C., Hsu, C.-H.: On the dynamic of air trap in the encapsulation process of microelectronics package. In: Proceedings of ANTEC’ 98 Conference (1998)Google Scholar
  10. 10.
    Zhou, T., Dreiza, M.: Stacked Die Package Design Guidelines. In: Proceedings of IMAPS Conference (2004)Google Scholar
  11. 11.
    Fukui, Y., Yano, Y., Juso, H., Matsune, Y., Miyata, K., Narai, A., Sota, Y., Takeda, Y., Fujita, K., Kada, M.: Triple-Chip Stacked CSP. In: IEEE 2000 International Electronic Components and Technology Conference. ISBN 0-7803-5908-9 (2000)Google Scholar
  12. 12.
    Kim, S.W., Turng, L.S.: Developments of three-dimensional computer-aided engineering simulation for injection molding. Institute of Physics Publishing. Model. Simul. Mater. Sci. Eng. 12(2004), S151–S173 (2004)CrossRefGoogle Scholar
  13. 13.
    Turng, L.S., Wang, V.W.: On the simulation of microelectronic encapsulation with epoxy molding compound. J. Reinf. Plastics Compos. 12, 506–519 (1993)CrossRefGoogle Scholar
  14. 14.
    Han, S., Wang, K.K.: Flow analysis in a cavity with lead frame during semiconductor chip encapsulation. In: Advance in Electronic Packaging, ASME EEP, vol. 10–11 (1995)Google Scholar
  15. 15.
    Nguyen, L.T.: Reactive flow simulation in transfer molding of IC Packages. In: Proceedings 43rd IEEE Electronic Components and Technology Conference 1993, pp. 375–390 (1993)Google Scholar

Conference Proceeding

  1. 16.
    Nguyen, L.: Flow simulation in IC chip encapsulation. Electronic Components and Technology Conference, Buena Vista (1994)Google Scholar
  2. 17.
    Nguyen, L., Jackson, J., Teo, C.H., Chillara, S., Asanasavest, C., Burke, T., Walberg, R., Lo, R., Weiler, P., Ho, D., Rauhut, H.: Wire Sweep Control with Mold Compound Formulation. In: 1997 Proceedings 47th Electronic Components and Technology, pp. 60–71 (1997)Google Scholar
  3. 18.
    Nguyen, L., Quentin, C.G., Lee, W.W.: Flow modeling and visualization of the transfer molding of plastic ball grid array packages. In: 1999 Electronic Components and Technology Conference, Santa Clara (1999)Google Scholar
  4. 19.
    Lee, M.M., Kim, J.Y., Yoo, M., Chung, J.Y., Lee, C.H.: Rheological characterization and full 3D mold flow simulation in multi-die stack CSP of chip array packaging. In: Electronic Components and Technology Conference, 1-4244-0152-6/06(2006)Google Scholar
  5. 20.
    Khalil Abdullah, M., Abdullah, M.Z., Mujeebu, M.A., Kamaruddin, S.: A study of effect of expoxy molding compound (EMC) rheology during encapsulation on stacked-CHIP scale packages (S-CSP). J. Reinf. Plast. Compos. 28, 2527–2538 (2008)Google Scholar
  6. 21.
    Khalil Abdullah, M., Abdullah, M.Z., Kamarudin, S., Ariff, Z.M.: Study of flow visualization in stacked-chip scale packages (S-CSP). Int. Commun. Heat Mass Transfer 34(7), 820–828 (2007)CrossRefGoogle Scholar
  7. 22.
    Khor, C.Y., Mujeebu, M.A., Abdullah, M.Z., Che Ani, F.: Finite volume based CFD Simulation of pressurized flip chip underfill encapsulation process, microelectronics reliability. Microelectron. Reliab. 50(1), 98–105 (2010)Google Scholar

Book Chapter

  1. 23.
    Modeling multiphase flow, FLUENT Documentation, Chapter 23Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Mior Firdaus Mior Abd Majid
    • 1
    Email author
  • Mohamad Sabri Mohamad Sidik
    • 1
  • Muhamad Husaini Abu Bakar
    • 1
  • Khairul Shahril Shafee
    • 1
  • Zainal Nazri Mohd Yusuf
    • 1
  • Mohamad Shukri Mohd Zain
    • 1
  • Mohd. Zulkifly Abdullah
    • 2
  1. 1.Universiti Kuala Lumpur, Malaysan Spanish InstituteKulimMalaysia
  2. 2.School of Mechanical and Aerospace EngineeringUniversiti Sains MalaysiaNibong TebalMalaysia

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