Advertisement

VISU: A Simple and Efficient Cache Coherence Protocol Based on Self-updating

  • Ximing He
  • Sheng Ma
  • Wenjie Liu
  • Sijiang Fan
  • Libo Huang
  • Zhiying Wang
  • Zhanyong Zhou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11337)

Abstract

Existing cache coherence protocols incur high overheads to shared memory systems and significantly reduce the system efficiency. For example, the widely used snooping protocol broadcasts messages at the expense of high network bandwidth overheads, and the directory protocol requires massive storage spaces to keep track of sharers. Furthermore, these coherence protocols have numerous transient states to cover various races, which increase the difficulty of implementation and verification. To mitigate these issues, this paper proposes a simple and efficient, two-state (Valid and Invalid) cache coherence protocol, VISU, for data-race-free programs. We adopt two distinct schemes for the private and shared data to simplify the design. Since the private data does not need to maintain coherence, we apply a simple write-back policy. For shared data, we leverage a write-through policy to make the last-level cache always hold the up-to-date data. A self-updating mechanism is deployed at synchronization points to update stale copies in L1 caches; this obviates the need for the broadcast communication or the directory.

Experimental results show that the VISU protocol achieves a significant reduction (31.0%) in the area overhead and obtains a better performance (2.9%) comparing with the sophisticated MESI directory protocol.

Keywords

Shared memory Cache coherence Self-updating VISU 

Notes

Acknowledgments

This work is supported by the National Natural Science Foundation of China(No.61672526,61572508,61472435) and Research Project of NUDT(ZK17-03-06).

References

  1. 1.
    Binkert, N.L., et al.: The gem5 simulator. SIGARCH Comput. Arch. News 39(2), 1–7 (2011)CrossRefGoogle Scholar
  2. 2.
    Adve, S.V., Hill, M.D.: Weak ordering-a new definition. In: International Symposium on Computer Architecture, vol. 18, no. 3, pp. 2–14 (1990)Google Scholar
  3. 3.
    Manson, J., Pugh, W., Adve, S.V.: The Java memory model. In: POPL (2005)Google Scholar
  4. 4.
    Boehm, H.-J., Adve, S.V.: Foundations of the C++ concurrency memory model. In: PLDI (2008)Google Scholar
  5. 5.
    Cuesta, B., et al.: Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks. IEEE Trans. Comput. 62(3), 482–495 (2013)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Kim, D., et al.: Subspace snooping: filtering snoops with operating system support. In: PACT (2010)Google Scholar
  7. 7.
    Hossain, H., Dwarkadas, S., Huang, M.C.: POPS: coherence protocol optimization for both private and shared data. In: PACT (2011)Google Scholar
  8. 8.
    Sorin, D.J., Hill, M.D., Wood, D.A.: A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool Publishers (2011)Google Scholar
  9. 9.
    Choi, B., et al. DeNovo: rethinking the memory hierarchy for disciplined parallelism. In: PACT (2011)Google Scholar
  10. 10.
    Sung, H., Komuravelli, R., Adve, S.V.: DeNovoND: efficient hardware support for disciplined non-determinism. In: ASPLOS (2013)Google Scholar
  11. 11.
    Ros, A., Kaxiras, S.: Complexity-effective multicore coherence. In: PACT (2012)Google Scholar
  12. 12.
    Agarwal, N., et al.: GARNET: a detailed on-chip network model inside a full-system simulator. In: ISPASS (2009)Google Scholar
  13. 13.
    Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: Architecting efficient interconnects for large caches with CACTI6.0. IEEE Micro 28(1), 69–79 (2008)CrossRefGoogle Scholar
  14. 14.
    Woo, S.C., et al.: The splash-2 programs: characterization and methodological considerations. In: ISCA 1995, pp. 24–36 (1995)Google Scholar
  15. 15.
    Nanda, A.K., Bhuyan, L.N.: A formal specification and verification technique for cache coherence protocols. In: ICPP (1992)Google Scholar
  16. 16.
    Kaxiras, S., Keramidas, G.: SARC coherence: scaling directory cache coherence in performance and power. IEEE Micro 30(5), 54–65 (2010)CrossRefGoogle Scholar
  17. 17.
    Ros, A., et al.: Efficient self-invalidation/self-downgrade for critical sections with relaxed semantics. IEEE Trans. Parallel Distrib. Syst. 28(12), 3413–3425 (2017)CrossRefGoogle Scholar
  18. 18.
    Sung, H., Komuravelli, R., Adve, S.V.: Denovond: efficient hardware for disciplined nondeterminism. IEEE Micro 34(3), 138–148 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Ximing He
    • 1
    • 2
  • Sheng Ma
    • 2
  • Wenjie Liu
    • 2
  • Sijiang Fan
    • 2
  • Libo Huang
    • 2
  • Zhiying Wang
    • 2
  • Zhanyong Zhou
    • 1
  1. 1.Bejing Aerospace Command Control CentreBeijingChina
  2. 2.The State Key Laboratory of High Performance ComputingNational University of Defense TechnologyChangshaChina

Personalised recommendations