Gaussian Process-Based Wafer-Level Correlation Modeling and Its Applications

  • Constantinos Xanthopoulos
  • Ke Huang
  • Ali Ahmadi
  • Nathan Kupp
  • John Carulli
  • Amit Nahar
  • Bob Orr
  • Michael Pass
  • Yiorgos MakrisEmail author


Semiconductor fabrication is one of the most intricate, multistep, human-made processes, taking place every day, producing trillions of transistors every second. The complexity of this manufacturing process naturally introduces variations with every stage affecting the produced devices differently. These variations can be observed at different granularity levels, within every die, across die at wafer level, across lots, and holistically for the entire production. Understanding and addressing such variations is the primary objective for many engineering roles, ranging from designers, to process engineers, and to test engineers. In this chapter, we focus on understanding and modeling wafer-level spatial and spatiotemporal variations through the use of Gaussian processes and we present various real-life applications of such modeling in test cost reduction, quality improvement, and yield learning.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Constantinos Xanthopoulos
    • 1
  • Ke Huang
    • 2
  • Ali Ahmadi
    • 1
  • Nathan Kupp
    • 3
  • John Carulli
    • 4
  • Amit Nahar
    • 5
  • Bob Orr
    • 5
  • Michael Pass
    • 5
  • Yiorgos Makris
    • 1
    Email author
  1. 1.The University of Texas at DallasRichardsonUSA
  2. 2.San Diego State UniversitySan DiegoUSA
  3. 3.Yale UniversityNew HavenUSA
  5. 5.Texas InstrumentsDallasUSA

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