Large-Scale Circuit Performance Modeling by Bayesian Model Fusion

  • Jun TaoEmail author
  • Fa Wang
  • Paolo Cachecho
  • Wangyang Zhang
  • Shupeng Sun
  • Xin LiEmail author
  • Rouwaida Kanj
  • Chenjie Gu
  • Xuan ZengEmail author


In this chapter, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AMS) circuits with consideration of large-scale process variations. The BMF technique is motivated by the fact that today’s AMS design cycle typically spans multiple stages (e.g., schematic design, layout design, first tape-out, second tape-out, etc.). Hence, we can reuse the simulation and/or measurement data collected at an early stage to facilitate efficient validation and tuning of AMS circuits with a minimal amount of data at the late stage. The efficacy of BMF is demonstrated by using several industrial circuit examples.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.State Key Laboratory of ASIC and System, School of MicroelectronicsFudan UniversityShanghaiChina
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA
  3. 3.Department of Electrical and Computer EngineeringAmerican University of BeirutBeirutLebanon
  4. 4.Cadence Design Systems, Inc.PittsburghUSA
  5. 5.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA
  6. 6.Strategic CAD LabsIntel CorporationHillsboroUSA

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