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System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)

  • Marwan Ammar
  • Ghaith Bany Hamad
  • Otmane Ait MohamedEmail author
  • Yvon Savaria
Chapter

Abstract

In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor. The proposed CTMC model is analyzed for different SEU injection scenarios and different bit-flip rates. Results demonstrate that the proposed approach can provide an accurate estimation of different metrics, such as Mean Time to Failure (MTTF), Mean Time to Recover(MTTR), Steady-State Availability (SSA), and the probability of failure for each SEU injection scenario in the system’s subcomponents. Furthermore, it is demonstrated that in comparison with existing simulation based analysis of fault impact evaluation, the presented approach is orders of magnitude faster in terms of analysis time.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Marwan Ammar
    • 1
  • Ghaith Bany Hamad
    • 1
  • Otmane Ait Mohamed
    • 1
    Email author
  • Yvon Savaria
    • 2
  1. 1.Concordia UniversityMontrealCanada
  2. 2.Polytechnique MontrealMontrealCanada

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