The functional verification of VHDL designs is accomplished through simulation using a test bench. A test bench is a VHDL system that instantiates the system to be tested as a component and then generates the input patterns and observes the outputs. VHDL provides a variety of capability to design test benches that can automate stimulus generation and provide automated output checking. These capabilities can be expanded by including packages that take advantage of reading/writing to external I/O. This chapter provides the details of VHDL’s built-in capabilities that allow test benches to be created and some examples of automated stimulus generation and using external files.