Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity

  • Yuya Sugie
  • Yuki Yoshida
  • Normann MertigEmail author
  • Takashi Takemoto
  • Hiroshi Teramoto
  • Atsuyoshi Nakamura
  • Ichigaku Takigawa
  • Shin-Ichi Minato
  • Masanao Yamaoka
  • Tamiki Komatsuzaki
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11324)


The emergence of new annealing hardware in the last decade and its potential for efficiently solving NP hard problems in quadratically unconstrained binary optimization (QUBO) by emulating the ground state search of an Ising model are likely to become an important paradigm in natural computing. Driven by the need to parsimoniously exploit the limited hardware resources of present day and near-term annealers, we present a heuristic for constructing graph minors by means of simulated annealing. We demonstrate that our algorithm improves on state of the art hardware embeddings, allowing for the representation of certain QUBO problems with up to 50% more binary variables.


Heuristics Graph minor Annealing QUBO 



It is our pleasure to thank Hirofumi Suzuki, Kazuhiro Kurita, and Shoya Takahashi for supporting the organization of the “Hokkaido University & Hitachi 2nd New-Concept Computing Contest 2017.”


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Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  1. 1.Hitachi Hokkaido University Laboratory, Center for Exploratory Research, Research and Development GroupHitachi, Ltd.SapporoJapan
  2. 2.Graduate School of Information Science and TechnologyHokkaido UniversitySapporoJapan
  3. 3.Department of Complexity Science and Engineering, Graduate School of Frontier SciencesThe University of TokyoKashiwaJapan
  4. 4.Research Center of Mathematics for Social Creativity, Research Institute for Electronic ScienceHokkaido UniversitySapporoJapan
  5. 5.PRESTO, Japan Science and Technology Agency (JST)Kawaguchi-shiJapan
  6. 6.Graduate School of InformaticsKyoto UniversityKyotoJapan

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