Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity
The emergence of new annealing hardware in the last decade and its potential for efficiently solving NP hard problems in quadratically unconstrained binary optimization (QUBO) by emulating the ground state search of an Ising model are likely to become an important paradigm in natural computing. Driven by the need to parsimoniously exploit the limited hardware resources of present day and near-term annealers, we present a heuristic for constructing graph minors by means of simulated annealing. We demonstrate that our algorithm improves on state of the art hardware embeddings, allowing for the representation of certain QUBO problems with up to 50% more binary variables.
KeywordsHeuristics Graph minor Annealing QUBO
It is our pleasure to thank Hirofumi Suzuki, Kazuhiro Kurita, and Shoya Takahashi for supporting the organization of the “Hokkaido University & Hitachi 2nd New-Concept Computing Contest 2017.”
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