Statistical Model Checking of Processor Systems in Various Interrupt Scenarios

  • Josef StrnadelEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11245)


Many practical, especially real-time, systems are expected to be predictable under various sources of unpredictability. To cope with the expectation, a system must be modeled and analyzed precisely for various operating conditions. This represents a problem that grows with the dynamics of the system and that must be, typically, solved before the system starts to operate. Due to the general complexity of the problem, this paper focuses just to processor based systems with interruptible executions. Their predictability analysis becomes more difficult especially when interrupts may occur at arbitrary times, suffer from arrival and servicing jitters, are subject to priorities, or may be nested and un/masked at run-time. Such a behavior of interrupts and executions has stochastic aspects and leads to the explosion of the number of situations to be considered. To cope with such a behavior, we propose a simulation model that relies on a network of stochastic timed automata and involves the above-mentioned behavioral aspects related to interrupts and executions. For a system, modeled by means of the automata, we show that the problem of analyzing its predictability may be efficiently solved by means of the statistical model checking.


Cpu System Interrupt Arrival Servicing Execution Priority Jitter Nesting Masking Late arrival Tail chaining Modeling Stochastic timed automaton Predictability Analysis Statistical model checking 


  1. 1.
    Kopetz, H.: Real-Time Systems - Design Principles for Distributed Embedded Applications. Real-Time Systems Series, 376 p. Springer, New York (2011). ISBN 978-1-4419-8236-0CrossRefGoogle Scholar
  2. 2.
    Buttazzo, G.: Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications, 376 p. Springer, New York (2011). ISBN 978-1-4614-0675-4CrossRefGoogle Scholar
  3. 3.
    Wilhelm, R., et al.: The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. 7(3), 36:1–36:53 (2008). Scholar
  4. 4.
    Strnadel, J., Rajnoha, P.: Reflecting RTOS model during WCET timing analysis: MSP430/FreeRTOS case study. Acta Electrotechnica et Informatica 12(4), 17–29 (2012).
  5. 5.
    Dalsgaard, A.E., Olesen, M.C., Toft, M., Hansen, R.R., Larsen, K.G.: METAMOC: modular execution time analysis using model checking. In: Lisper, B. (ed.) 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010). OASIcs, vol. 15, pp. 113–123. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany (2010).
  6. 6.
    Cassez, F., de Aledo, P.G., Jensen, P.G.: WUPPAAL: computation of worst-case execution-time for binary programs with UPPAAL. In: Aceto, L., Bacci, G., Bacci, G., Ingólfsdóttir, A., Legay, A., Mardare, R. (eds.) Models, Algorithms, Logics and Tools. LNCS, vol. 10460, pp. 560–577. Springer, Cham (2017). Scholar
  7. 7.
    Regehr, J., Duongsaa, U.: Preventing interrupt overload. In: Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools For Embedded Systems, New York, United States, pp. 50–58. ACM (2005). Scholar
  8. 8.
    Pellizzoni, R.: Predictable and monitored execution for cots-based real-time embedded systems, Ph.D. thesis, Bonn, Germany. University of Illinois at Urbana-Champaign (2010)Google Scholar
  9. 9.
    Amiri, J.E., Kargahi, M.: A predictable interrupt management policy for real-time operating systems. In: Proceedings of CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST), pp. 1–8. IEEE (2015).
  10. 10.
    Lynx. Lynx Software Technologies Patented Technology Speeds Handling of Hardware Events (2018).
  11. 11.
    Leyva-del Foyo, L.E., Mejia-Alvarez, P., de Niz, D.: Integrated task and interrupt management for real-time systems. ACM Trans. Embed. Comput. Syst. 11(2), 32:1–32:31 (2012). Scholar
  12. 12.
    Cottet, F., Delacroix, J., Kaiser, C., Mammeri, Z.: Scheduling in Real-Time Systems. Wiley, New York (2001). ISBN 978-0-470-84766-4Google Scholar
  13. 13.
    Automotive Open System Architecture GbR (AUTOSAR). Specification of Operating System. Technical report (2018).
  14. 14.
    Strnadel, J.: Predictability analysis of interruptible systems by statistical model checking. IEEE Des. Test 35(2), 57–63 (2018). Scholar
  15. 15.
    Chattopadhyay, S., Tresina, M., Narayan, S.: Worst case execution time analysis of automotive software. Procedia Eng. 30, 983–988 (2012). Scholar
  16. 16.
    Kotker, J., Sadigh, D., Seshia, S.A.: Timing analysis of interrupt-driven programs under context bounds. In: Proceedings of Formal Methods in Computer-Aided Design (FMCAD), pp. 81–90 (2012)Google Scholar
  17. 17.
    Kidd, N., Jagannathan, S., Vitek, J.: One stack to run them all. In: van de Pol, J., Weber, M. (eds.) SPIN 2010. LNCS, vol. 6349, pp. 245–261. Springer, Heidelberg (2010). Scholar
  18. 18.
    Wu, X., Wen, Y., Chen, L., Dong, W., Wang, J.: Data race detection for interrupt-driven programs via bounded model checking. In: Proceedings of the 2013 IEEE Seventh International Conference on Software Security and Reliability Companion, SERE-C 2013, Washington, DC, USA pp. 204–210. IEEE CS (2013).
  19. 19.
    Kroening, D., Liang, L., Melham, T., Schrammel, P., Tautschnig, M.: Effective verification of low-level software with nested interrupts. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, ser. DATE 2015, Jose, CA, USA, pp. 229–234. EDA Consortium (2015).
  20. 20.
    Baier, C., Katoen, J.-P.: Principles of Model Checking, ser. Representation and Mind. MIT Press, London (2008).
  21. 21.
    David, A., Larsen, K.G., Legay, A., Mikucionis, M., Poulsen, D.: UPPAAL SMC tutorial. Int. J. Softw. Tools Technol. Transf. 17(4), 397–415 (2015). Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  1. 1.Faculty of Information Technology, Centre of Excellence IT4InnovationsBrno University of TechnologyBrnoCzech Republic

Personalised recommendations