Comparative Analysis of Digital Circuits Using 16 nm FinFET and HKMG PTM Models

  • Satish Masthenahally Nachappa
  • A. S. Jeevitha
  • K. S. Vasundara Patel
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 886)


Low Power VLSI design has become the most important challenge of present chip designs. Advances in chip fabrication have made possible to design chips at high integration and fast performance. Reducing power consumption and increasing noise margin have become two major concerns in every stage of SRAM designs. In this paper the 6T and 8T SRAM cells are constructed using High-K Metal Gate and FinFET for low power embedded memory applications. These SRAM cells’ performance are analyzed and compared in terms of basic parameters, such as power consumption and static noise margin (SNM).


SRAM High-K Metal Gate FinFET Low power Leakage current Static noise margin 


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Satish Masthenahally Nachappa
    • 1
  • A. S. Jeevitha
    • 2
  • K. S. Vasundara Patel
    • 2
  1. 1.Department of Electronics and CommunicationMiddle East CollegeMuscatOman
  2. 2.Department of ECEBMS College of EngineeringBengaluruIndia

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