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Flow Characteristic-Aware Cache Replacement Policy for Packet Processing Cache

  • Hayato Yamaki
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 886)

Abstract

The increase in internet traffic amount becomes a serious problem for routers from the aspects of the packet processing throughput and the power consumption. Packet processing cache (PPC) is a promising approach to meet the requirements. PPC can reduce the number of accesses to ternary content addressable memory (TCAM), which accounts for a large percentage of the power consumption of a router, by storing the TCAM lookup results into a cache memory and reusing them. For PPC, the cache miss rate has significant impact on the throughput and the power consumption. Thus, reducing the number of cache misses is a main concern for PPC. In this study, we first analyze the elephant flows and mice flows in networks to reveal the packet behavior in PPC and propose a novel cache replacement policy based on the analysis. Hit dominance cache (HDC), proposed in this paper, gives high priority to the elephant flows and evicts the mice flows rapidly. Our simulation showed HDC can reduce the number of cache misses in PPC by up to 29.1% compared to conventional 4-way LRU PPC. In addition, we estimated the hardware cost of HDC by using Verilog-HDL and showed that it is comparable to those of 4-way LRU though HDC performs as if the cache was composed of 8-way set associative cache.

Keywords

Core router Packet processing Cache replacement policy 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of Computer and Network EngineeringThe University of Electro-CommunicationsChofuJapan

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