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Design of 14-Bit SAR ADC with Improved Linearity and Signal Dependent Charge Re-Cycling

  • A. R. Athira Nair
  • K. Nisha Jose
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

This paper presents two digital-to-analog (DAC) switching schemes aiming at reducing the non-linearity and a signal dependent charge re-cycling scheme aiming at saving the energy consumption for a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed method can improve integral non-linearity (INL) from 0.19 to 0.34 LSB value and differential non-linearity (DNL) value from 0.01 to 0.25 LSB. Furthermore the signal dependent charge re-cycling scheme includes a modified capacitive-DAC (CDAC) which retain MSB voltage of previous sample and utilize it throughout the successive conversions. This avoids the MSB capacitors from random switching and minimizes energy consumed in SAR logic and comparator circuit.

Keywords

Analog-to- digital converter(ADC) Capacitive digital-to-analog converter (CDAC) Charge re-cycling Digital-to-analog converter (DAC) Differential non-linearity (DNL) Integral non-linearity (INL) Successive approximation register (SAR) ADC 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringSree Chithra Thirunal College of EngineeringTrivandrumIndia

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