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An Optimized Packet Transceiver Design for Ethernet-MAC Layer Based on FPGA

  • S. P. GuruprasadEmail author
  • B. S. Chandrasekar
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

The fully functional Ethernet-MAC layer is designed in accordance with IEEE 802.3 standards. The Proposed Ethernet MAC design is based on packet transceiver architecture for transmitting and receiving a packets and ensuring that the received packets are indeed valid. This design mainly includes Transmitter and Receiver-Finite state machines (FSM), FIFO’s, Cyclic Redundancy check (CRC), and padding modules. It’s compatible with input-output signals of Physical layer, the management module, and MII/RMII/GMII/RGMII interface of MAC Core. The design is extended to configure half duplex and full duplex mode based on the request. The design supports 10/100/1000 Mb/s and 1 Gb/s accessible speed and also extended to 10 Gb/s with parametrizable FIFO’s and configurable CRC with Tx and Rx state machines. The design is adaptable and is flexible to any FPGA vendors. It is synthesized on Xilinx platform by Verilog coding, simulated by ModelSim simulator and implemented on Virtex-7 FPGA Device. The proposed Ethernet-MAC Layer is compared with Xilinx Trimode Ethernet MAC Core (TEMAC) with respect to area resources with an optimization of 32.85% in slices and 24.88% LUT’s. The results have been encouraging.

Keywords

Ethernet MAC IEEE 802.3 FPGA CRC Verilog Physical layer MDIO RGMII 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of ECEJain UniversityBangaloreIndia
  2. 2.CVLIJain UniversityBangaloreIndia

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