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Design of Low Power RSC Encoder Using Reversible Logic

  • J. Aishvarya
  • P. S. N. V. V. Sai Manindra
  • P. Sathya Priya
  • Kruthi Vaseeshwar Rao
  • E. PrabhuEmail author
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

The principal theme in present world of electronic is low power design. In modern technologies, low power design has drawn significant concern due to increasing transistor counts, higher speed of operations and clock frequencies. Reversible logic plays a vital role when VLSI circuits with minimal power dissipation are considered. It has the ability to decrease the power dissipation by recuperating bit loss from its distinctive one to one mapping. This paper presents a novel design of Recursive Systematic Convolutional (RSC) Encoder using the existing reversible gates. The proposed RSC encoder is coded in Verilog-HDL and synthesized in synopsis DC tool (90 nm library). The power analysis report shows that the proposed RSC encoder circuit dissipates less power when compared to the conventional one.

Keywords

Low power RSC encoder Reversible logic 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • J. Aishvarya
    • 1
  • P. S. N. V. V. Sai Manindra
    • 1
  • P. Sathya Priya
    • 1
  • Kruthi Vaseeshwar Rao
    • 1
  • E. Prabhu
    • 1
    Email author
  1. 1.Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa VidyapeethamAmrita UniversityCoimbatoreIndia

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