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Quad-Rail Sense-Amplifier Based NoC Router Design

  • N. AshokkumarEmail author
  • P. Nagarajan
  • N. Vithyalakshmi
  • P. Venkataramana
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

Sense-amplifier half-buffer method with quad-rail (i.e., 1-of-4) data programming is focus about power and Low area Overhead in Low Power applications in asynchronous logic manner. The planned SAHB method is besieged for energy effectual and of asynchronous NoC (Network-On-Chip) planning of router strategy. The foremost characteristics of quad-rail SAHB method is specified as priority manner. The primary one is, quad-rail SAHB is planned to utilize the four ports for Asynchronous Network-On-Chip (NoC) router output way of delivery and here diminishing the total amount of transistors and region area overhead. Secondary one is the SAHB instructs one port away from four ports for two bit data circulation. The digit of transistor switching occurrence and also vivacious power rakishness. Finally, the SAHB combine by Delay Incentive rules, to plan the router attributes lofty functioning sturdiness follow up the temperature-voltage variations. The proposed technique is to execute the ANoC router plan for 18 bit. The benchmark of the projected SAHB- quad-rail ANoC router description to achieve 32% lesser area. The dissipation of energy level is upto 50%.

Keywords

Network-on-chip router (Asynchronous) Energy efficient CLSA (control logic cum sense amplifier) Data encoding Quasi-delay insensitive (QDI) 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • N. Ashokkumar
    • 1
    Email author
  • P. Nagarajan
    • 1
  • N. Vithyalakshmi
    • 1
  • P. Venkataramana
    • 1
  1. 1.Sree Vidyanikethan Engineering CollegeTirupatiIndia

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