Design and Analysis of a 4-Bit Flash ADC Architecture with Modified Comparator

  • Anil KhatakEmail author
  • Manoj Kumar
  • Sanjeev Dhull
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)


A 4-BIT flash-ADC is simulated in this work in 90 nm CMOS technology by altering the comparator structure. Two comparators are employed for analysis one is a comparator with cross-coupled inverters & other is a comparator with regenerative latch. Simulations are executed by varying the supply voltage & channel width for different temperatures. Power consumption is then observed & recorded ideally at 0.7 V supply voltage & 1 µm channel length. The minimum power consumption with comparator (cross-coupled) is 14.6 µW at −10 °C & maximum power consumption of 17.94 µW at 50 °C. Then by altering the comparator to comparator (regenerative latch) the minimum power consumption of 192.1 µW at −10 °C & maximum power consumption of 215.5 µW at 50 °C is recorded. Temperature variation leads to the further increment in power consumption. Simulations are executed by employing SPICE based on 90 nm CMOS technology.


Analog to Digital Converter (ADC) Encoder Multiplexer Complementary Ultra Deep Submicron (UDSM) 


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© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of BMEGJUS&THisarIndia
  2. 2.USICT, Guru Gobind Singh Indraprastha UniversityNew DelhiIndia
  3. 3.Department of ECEGJUS&THisarIndia

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