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Design and Analysis of a 4-Bit Flash ADC Architecture with Modified Comparator

  • Anil KhatakEmail author
  • Manoj Kumar
  • Sanjeev Dhull
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

A 4-BIT flash-ADC is simulated in this work in 90 nm CMOS technology by altering the comparator structure. Two comparators are employed for analysis one is a comparator with cross-coupled inverters & other is a comparator with regenerative latch. Simulations are executed by varying the supply voltage & channel width for different temperatures. Power consumption is then observed & recorded ideally at 0.7 V supply voltage & 1 µm channel length. The minimum power consumption with comparator (cross-coupled) is 14.6 µW at −10 °C & maximum power consumption of 17.94 µW at 50 °C. Then by altering the comparator to comparator (regenerative latch) the minimum power consumption of 192.1 µW at −10 °C & maximum power consumption of 215.5 µW at 50 °C is recorded. Temperature variation leads to the further increment in power consumption. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

Keywords

Analog to Digital Converter (ADC) Encoder Multiplexer Complementary Ultra Deep Submicron (UDSM) 

References

  1. 1.
    Zarifi, M.H., Frounchi, J., Farshchi, S., Judy, J.W.: A low-power, low-noise neural-signal amplifier circuit in 90-nm CMOS. In: Proceedings of the 30th IEEE Engineering in Medicine and Biology Conference (2008)Google Scholar
  2. 2.
    Khatak, A., Dhull, S., Taleja, M.K.: A study on advanced high speed and ultra low power ADC architectures. Indian J. Sci. Technol. 10 (2017) CrossRefGoogle Scholar
  3. 3.
    Rostami, A., Zarifi, M.H., Kuze Kanani, Z.D., Sobhi, J.: A 12 bit, 80 Msamples/s, pipeline analog to digital converter. In: Proceeding of 5th İnternational Conference on Electrical and Electronics Engineering, Bursa, Turkey (2007)Google Scholar
  4. 4.
    Grace, C.R., Hurst, P.J., Lewis, S.H.: A 12-bit, 80-Msample/s pipeline analog to digital converter with bootstrapped digital calibration. IEEE J. Solid-State Circuits E 40(5), 1038–1046 (2005)CrossRefGoogle Scholar
  5. 5.
    Farshchi, S., Markovic, D., Pamarti, S., Razavi, B., Judy, J.W.: Towards neuromote: A single-chip, 100-channel, neural signal acquisition, processing, and telemetry device. In: 29th IEEE Engineering in Medicine and Biology Conference (2007)Google Scholar
  6. 6.
    Scott, M.D., Boser, B.E., Pister, K.S.J.: An ultra-low energy ADC for smart dust. IEEE J. Solid-State Circuits 38(7), 1123–1129 (2003)CrossRefGoogle Scholar
  7. 7.
    Yang, W., Kelly, D., Mehr, I., Sayuk, M., Singer, L.: A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J. Solid-State Circuits 36(12), 1931–1936 (2001)CrossRefGoogle Scholar
  8. 8.
    Abo, A., Gray, P.R.: A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(5), 599–606 (1999)CrossRefGoogle Scholar
  9. 9.
    Márquez, F., Muñoz, F., Carvajal, R.G., García-Oya, J.R., López-Morillo, E., Torralba, A., Galán, J.: A novel autozeroing technique for flash Analog-to-Digital converters. Integr. VLSI J. 47, 23–29 (2014)CrossRefGoogle Scholar
  10. 10.
    Hasan, M., Shen, H.-H.P., Allee, D.R., Pennell, M.: A behavioural model of a 1.8-V flash A/D converter based on device parameters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1) (2000)CrossRefGoogle Scholar
  11. 11.
    Matsuno, J., Hosoya, M., Furuta, M., Itakura, T.: A 3-GS/s 5-bit flash ADC with wideband input buffer amplifier. In: International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April 2013, pp. 1–4 (2013)Google Scholar
  12. 12.
    Chen, Y., Lai, J.S., Lin, Z.M.: A 6-Bit 3-GS/s two-channel time interleaved interpolating flash ADC. In: IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp. 1–4, June 2013Google Scholar
  13. 13.
    Lee, J.I., Song, J.-I.: Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count. In: IEEE Region 10 Conference TENCON, pp. 1–4, October 2013 (2013)Google Scholar
  14. 14.
    Damghanian, M., Azhari, S.J.: A low power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications. Integr. VLSI J. (2017). http://dx.doi.org/10.1016/j.vlsi.2017.01.006
  15. 15.
    Yoo, J., Choi, K., Lee, D.: Comparator generation and selection for highly linear CMOS flash analog-to-digital converter. Analog Integr. Circuits Signal Process. 35, 179–187 (2003)CrossRefGoogle Scholar
  16. 16.
    Lee, J.I., Song, J.I.: Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count. In: 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013), Xi’an, pp. 1–4 (2013).  https://doi.org/10.1109/tencon.2013.6718487
  17. 17.
    Khatak, A., Kumar, M., Dhull, S.: Comparative analysis of comparators in 90 nm CMOS Technology. In: 1st IEEE International Conference on Power Energy, Environment & Intelligent Control (PEEIC 2018), pp. 1–8 (2018)Google Scholar
  18. 18.
    Lotfi, R., Majidi, R., Nejad, R.M., Serdijn, W.A.: An ultra–low-power 10-bit 100 kS/s successive approximation analog to digital converter. In: Proceedings of the IEEE International Symposium on Circuits Systems, pp. 1117–1120, May 2009Google Scholar
  19. 19.
    Khatak, A., Kumar, M., Dhull, S.: Analysis of CMOS comparator in 90 nm technology with different power reduction techniques. Int. J. Electr. Comput. Eng. 8 (2018). http://doi.org/10.11591/ijece.v8i6.pp%25p
  20. 20.
    Chuang, Y.-J., Ou, H.-H., Liu, B.-D.: A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter. In: IEEE VLSITSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), April 27–29, 2005, pp. 315–318. (2015).  https://doi.org/10.1109/vdat.2005.1500084
  21. 21.
    Pilipko, M.M., Morozov, D.V., Budanov, D.O.: Comparative analysis of CMOS circuits of a thermometer-to-binary encoder for ıntegrated flash analog-to-digital converters. Russ. Microelectr. 46(1) (2017)CrossRefGoogle Scholar
  22. 22.
    Tom, T., Mahapatra, V.K.: Low Power Reconfigurable Encoder for Flash ADCs, Global Colloquium. In: Recent Advancement and Effectual Researches in Engineering, Science and Technology (RAEREST 2016) (2016)Google Scholar
  23. 23.
    Katic, N., Cojbasic, R., Schmid, A., Leblebici, Y.: A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder. Microelectr. J. (2015)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of BMEGJUS&THisarIndia
  2. 2.USICT, Guru Gobind Singh Indraprastha UniversityNew DelhiIndia
  3. 3.Department of ECEGJUS&THisarIndia

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