A Novel Approach to Optimize Design of n-Bit AES Using Reversible Logic

  • Hongal RohiniEmail author
  • A. C. Pavankumar
  • Rajashekhar B. Shettar
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)


In recent years security of the data plays a pivotal role in the development of future networks which are feasible, fast and highly secured. Cryptography is one of the significant area to support network security, including converting data into encrypted message. AES is a symmetric cryptographic algorithm which is faster with excellent security and less memory computations. Even though AES consumes significantly low power, it has side channel attack which relies on the power analysis of the cryptosystem. Reversible logic has been evolved over the time with significant reduction in power dissipation. So side channel attack can be addressed with reversible logic implementation. AES has main applications in wireless communication and video surveillance systems. This paper presents a generalized approach to implement AES using reversible logic with different keylength having plaintext of 128 bit. This algorithm consists of three main rounds which are added prior to the standard algorithm. The AES algorithm of 128, 192, 256 bits for cryptographic procedure has been simulated and verified on FPGA Virtex 5 ML505 board using Xilinx chipscope using reversible logic. The proposed algorithm is compared with standard AES in terms of hardware requirements and results in 10% improvement in hardware requirements for AES-128 bit. Thus one round is eliminated compared to standard AES algorithm by maintaining same security.


Cryptanalysis Message digest Reversible logic SHA 


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Hongal Rohini
    • 1
    Email author
  • A. C. Pavankumar
    • 1
  • Rajashekhar B. Shettar
    • 1
  1. 1.Electronics and Communication DepartmentBVBCETHubballiIndia

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