Advertisement

Replacing Store Buffers by Load Buffers in TSO

  • Parosh Aziz AbdullaEmail author
  • Mohamed Faouzi Atig
  • Ahmed Bouajjani
  • Tuan Phong Ngo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11181)

Abstract

We consider the weak memory model of Total Store Ordering (TSO). In the classical definition of TSO, an unbounded buffer is inserted between each process and the shared memory. The buffers contains pending store operations of the processes. We introduce a new model where we replace the store buffers by load buffers. In contrast to the classical model, the buffers now contain load operations. We show that the models have equivalent behaviors in the sense that the processes reach identical sets of states when the input program is run under the two models.

Keywords

Program verification Weak memory models TSO 

References

  1. 1.
    Abdulla, P.A., Aronis, S., Atig, M.F., Jonsson, B., Leonardsson, C., Sagonas, K.: Stateless model checking for TSO and PSO. In: Baier, C., Tinelli, C. (eds.) TACAS 2015. LNCS, vol. 9035, pp. 353–367. Springer, Heidelberg (2015).  https://doi.org/10.1007/978-3-662-46681-0_28CrossRefzbMATHGoogle Scholar
  2. 2.
    Abdulla, P.A., Atig, M.F., Chen, Y.-F., Leonardsson, C., Rezine, A.: Counter-example guided fence insertion under TSO. In: Flanagan, C., König, B. (eds.) TACAS 2012. LNCS, vol. 7214, pp. 204–219. Springer, Heidelberg (2012).  https://doi.org/10.1007/978-3-642-28756-5_15CrossRefGoogle Scholar
  3. 3.
    Abdulla, P.A., Atig, M.F., Chen, Y.-F., Leonardsson, C., Rezine, A.: Memorax, a precise and sound tool for automatic fence insertion under TSO. In: Piterman, N., Smolka, S.A. (eds.) TACAS 2013. LNCS, vol. 7795, pp. 530–536. Springer, Heidelberg (2013).  https://doi.org/10.1007/978-3-642-36742-7_37CrossRefGoogle Scholar
  4. 4.
    Abdulla, P.A., Atig, M.F., Ngo, T.-P.: The best of both worlds: trading efficiency and optimality in fence insertion for TSO. In: Vitek, J. (ed.) ESOP 2015. LNCS, vol. 9032, pp. 308–332. Springer, Heidelberg (2015).  https://doi.org/10.1007/978-3-662-46669-8_13CrossRefGoogle Scholar
  5. 5.
    Abdulla, P., Cerans, K., Jonsson, B., Tsay, Y.: General decidability theorems for infinite-state systems. In: LICS 1996, pp. 313–321. IEEE Computer Society (1996)Google Scholar
  6. 6.
    Abdulla, P.A.: Well (and better) quasi-ordered transition systems. Bull. Symb. Log. 16(4), 457–515 (2010)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Abdulla, P.A., Atig, M.F., Bouajjani, A., Ngo, T.P.: Context-bounded analysis for POWER. In: Legay, A., Margaria, T. (eds.) TACAS 2017. LNCS, vol. 10206, pp. 56–74. Springer, Heidelberg (2017).  https://doi.org/10.1007/978-3-662-54580-5_4CrossRefGoogle Scholar
  8. 8.
    Abdulla, P.A., Atig, M.F., Chen, Y.-F., Leonardsson, C., Rezine, A.: Automatic fence insertion in integer programs via predicate abstraction. In: Miné, A., Schmidt, D. (eds.) SAS 2012. LNCS, vol. 7460, pp. 164–180. Springer, Heidelberg (2012).  https://doi.org/10.1007/978-3-642-33125-1_13CrossRefGoogle Scholar
  9. 9.
    Abdulla, P.A., Atig, M.F., Jonsson, B., Leonardsson, C.: Stateless model checking for POWER. In: Chaudhuri, S., Farzan, A. (eds.) CAV 2016. LNCS, vol. 9780, pp. 134–156. Springer, Cham (2016).  https://doi.org/10.1007/978-3-319-41540-6_8CrossRefGoogle Scholar
  10. 10.
    Abdulla, P.A., Atig, M.F., Lång, M., Ngo, T.P.: Precise and sound automatic fence insertion procedure under PSO. In: Bouajjani, A., Fauconnier, H. (eds.) NETYS 2015. LNCS, vol. 9466, pp. 32–47. Springer, Cham (2015).  https://doi.org/10.1007/978-3-319-26850-7_3CrossRefGoogle Scholar
  11. 11.
    Alglave, J., Kroening, D., Nimal, V., Tautschnig, M.: Software verification for weak memory via program transformation. In: Felleisen, M., Gardner, P. (eds.) ESOP 2013. LNCS, vol. 7792, pp. 512–532. Springer, Heidelberg (2013).  https://doi.org/10.1007/978-3-642-37036-6_28CrossRefGoogle Scholar
  12. 12.
    Alglave, J., Kroening, D., Tautschnig, M.: Partial orders for efficient bounded model checking of concurrent software. In: Sharygina, N., Veith, H. (eds.) CAV 2013. LNCS, vol. 8044, pp. 141–157. Springer, Heidelberg (2013).  https://doi.org/10.1007/978-3-642-39799-8_9CrossRefzbMATHGoogle Scholar
  13. 13.
    Alglave, J., Maranget, L., Tautschnig, M.: Herding cats: modelling, simulation, testing, and data mining for weak memory. ACM TOPLAS 36(2), 7:1–7:4 (2014)CrossRefGoogle Scholar
  14. 14.
    ARM: ARM architecture reference manual ARMv7-A and ARMv7-R edition (2012)Google Scholar
  15. 15.
    ISO/IEC 14882:2014. Programming language C++ (2014)Google Scholar
  16. 16.
    Atig, M.F., Bouajjani, A., Burckhardt, S., Musuvathi, M.: On the verification problem for weak memory models. In: POPL (2010)Google Scholar
  17. 17.
    Atig, M.F., Bouajjani, A., Burckhardt, S., Musuvathi, M.: What’s decidable about weak memory models? In: Seidl, H. (ed.) ESOP 2012. LNCS, vol. 7211, pp. 26–46. Springer, Heidelberg (2012).  https://doi.org/10.1007/978-3-642-28869-2_2CrossRefGoogle Scholar
  18. 18.
    Atig, M.F., Bouajjani, A., Parlato, G.: Getting rid of store-buffers in TSO analysis. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol. 6806, pp. 99–115. Springer, Heidelberg (2011).  https://doi.org/10.1007/978-3-642-22110-1_9CrossRefGoogle Scholar
  19. 19.
    Bouajjani, A., Derevenetc, E., Meyer, R.: Checking and enforcing robustness against TSO. In: Felleisen, M., Gardner, P. (eds.) ESOP 2013. LNCS, vol. 7792, pp. 533–553. Springer, Heidelberg (2013).  https://doi.org/10.1007/978-3-642-37036-6_29CrossRefzbMATHGoogle Scholar
  20. 20.
    Burckhardt, S., Alur, R., Martin, M.M.K.: CheckFence: checking consistency of concurrent data types on relaxed memory models. In: PLDI, pp. 12–21. ACM (2007)Google Scholar
  21. 21.
    Burckhardt, S., Musuvathi, M.: Effective program verification for relaxed memory models. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 107–120. Springer, Heidelberg (2008).  https://doi.org/10.1007/978-3-540-70545-1_12CrossRefzbMATHGoogle Scholar
  22. 22.
    Burnim, J., Sen, K., Stergiou, C.: Testing concurrent programs on relaxed memory models. In: ISSTA, pp. 122–132. ACM (2011)Google Scholar
  23. 23.
    Dan, A.M., Meshman, Y., Vechev, M., Yahav, E.: Predicate abstraction for relaxed memory models. In: Logozzo, F., Fähndrich, M. (eds.) SAS 2013. LNCS, vol. 7935, pp. 84–104. Springer, Heidelberg (2013).  https://doi.org/10.1007/978-3-642-38856-9_7CrossRefGoogle Scholar
  24. 24.
    Dan, A., Meshman, Y., Vechev, M., Yahav, E.: Effective abstractions for verification under relaxed memory models. Comput. Lang. Syst. Struct. 47(Part 1), 62–76 (2017)zbMATHGoogle Scholar
  25. 25.
    Demsky, B., Lam, P.: Satcheck: sat-directed stateless model checking for SC and TSO. In: OOPSLA 2015, pp. 20–36. ACM (2015)Google Scholar
  26. 26.
    Derevenetc, E., Meyer, R.: Robustness against power is PSpace-complete. In: Esparza, J., Fraigniaud, P., Husfeldt, T., Koutsoupias, E. (eds.) ICALP 2014. LNCS, vol. 8573, pp. 158–170. Springer, Heidelberg (2014).  https://doi.org/10.1007/978-3-662-43951-7_14CrossRefGoogle Scholar
  27. 27.
    Finkel, A., Schnoebelen, P.: Well-structured transition systems everywhere!. Theor. Comput. Sci. 256(1–2), 63–92 (2001)MathSciNetCrossRefGoogle Scholar
  28. 28.
    He, M., Vafeiadis, V., Qin, S., Ferreira, J.F.: Reasoning about fences and relaxed atomics. In: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, 17–19 February 2016, pp. 520–527 (2016)Google Scholar
  29. 29.
    Huang, S., Huang, J.: Maximal causality reduction for TSO and PSO. OOPSLA, pp. 447–461 (2016)Google Scholar
  30. 30.
    IBM (ed.): Power ISA v. 2.05 (2007)Google Scholar
  31. 31.
    Inc, I.: Intel™64 and IA-32 Architectures Software Developer’s ManualsGoogle Scholar
  32. 32.
    Kuperstein, M., Vechev, M.T., Yahav, E.: Automatic inference of memory fences. In: FMCAD, pp. 111–119. IEEE (2010)Google Scholar
  33. 33.
    Kuperstein, M., Vechev, M.T., Yahav, E.: Partial-coherence abstractions for relaxed memory models. In: PLDI, pp. 187–198. ACM (2011)Google Scholar
  34. 34.
    Lahav, O., Vafeiadis, V.: Owicki-Gries reasoning for weak memory models. In: Halldórsson, M.M., Iwama, K., Kobayashi, N., Speckmann, B. (eds.) ICALP 2015. LNCS, vol. 9135, pp. 311–323. Springer, Heidelberg (2015).  https://doi.org/10.1007/978-3-662-47666-6_25CrossRefGoogle Scholar
  35. 35.
    Lahav, O., Vafeiadis, V.: Explaining relaxed memory models with program transformations. In: Fitzgerald, J., Heitmeyer, C., Gnesi, S., Philippou, A. (eds.) FM 2016. LNCS, vol. 9995, pp. 479–495. Springer, Cham (2016).  https://doi.org/10.1007/978-3-319-48989-6_29CrossRefGoogle Scholar
  36. 36.
    Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput. C–28(9), 690–691 (1979)CrossRefGoogle Scholar
  37. 37.
    Liu, F., Nedev, N., Prisadnikov, N., Vechev, M.T., Yahav, E.: Dynamic synthesis for relaxed memory models. In: PLDI 2012, pp. 429–440 (2012)Google Scholar
  38. 38.
    Mador-Haim, S., et al.: An axiomatic memory model for POWER multiprocessors. In: Madhusudan, P., Seshia, S.A. (eds.) CAV 2012. LNCS, vol. 7358, pp. 495–512. Springer, Heidelberg (2012).  https://doi.org/10.1007/978-3-642-31424-7_36CrossRefGoogle Scholar
  39. 39.
    Manson, J., Pugh, W., Adve, S.V.: The Java memory model. In: POPL2005, pp. 378–391. ACM (2005)Google Scholar
  40. 40.
    McKenney, P.E.: Memory ordering in modern microprocessors, part II. Linux J. 137, 5 (2005)Google Scholar
  41. 41.
    Nieplocha, J., Carpenter, B.: ARMCI: a portable remote memory copy library for distributed array libraries and compiler run-time systems. In: Rolim, J., et al. (eds.) IPPS 1999. LNCS, vol. 1586, pp. 533–546. Springer, Heidelberg (1999).  https://doi.org/10.1007/BFb0097937CrossRefGoogle Scholar
  42. 42.
    Owens, S., Sarkar, S., Sewell, P.: A better x86 memory model: x86-TSO. In: Berghofer, S., Nipkow, T., Urban, C., Wenzel, M. (eds.) TPHOLs 2009. LNCS, vol. 5674, pp. 391–407. Springer, Heidelberg (2009).  https://doi.org/10.1007/978-3-642-03359-9_27CrossRefGoogle Scholar
  43. 43.
    Owens, S., Sarkar, S., Sewell, P.: A better x86 memory model: x86-TSO (extended version). Technical report. UCAM-CL-TR-745, University of Cambridge (2009)Google Scholar
  44. 44.
    Sewell, P., Sarkar, S., Owens, S., Nardelli, F.Z., Myreen, M.O.: x86-tso: a rigorous and usable programmer’s model for x86 multiprocessors. CACM 53, 89–97 (2010)CrossRefGoogle Scholar
  45. 45.
    Tomasco, E., Lam, T.N., Fischer, B., Torre, S.L., Parlato, G.: Embedding weak memory models within eager sequentialization, October 2016. http://eprints.soton.ac.uk/402285/
  46. 46.
    Tomasco, E., Lam, T.N., Inverso, O., Fischer, B., Torre, S.L., Parlato, G.: Lazy sequentialization for TSO and PSO via shared memory abstractions. In: FMCAD16, pp. 193–200 (2016)Google Scholar
  47. 47.
    Travkin, O., Wehrheim, H.: Verification of concurrent programs on weak memory models. In: Sampaio, A., Wang, F. (eds.) ICTAC 2016. LNCS, vol. 9965, pp. 3–24. Springer, Cham (2016).  https://doi.org/10.1007/978-3-319-46750-4_1CrossRefzbMATHGoogle Scholar
  48. 48.
    Vafeiadis, V.: Separation logic for weak memory models. In: Proceedings of the Programming Languages Mentoring Workshop, PLMW@POPL 2015, Mumbai, India, 14 January 2015, p. 11:1 (2015)Google Scholar
  49. 49.
    Weaver, D., Germond, T. (eds.): The SPARC Architecture Manual Version 9. PTR Prentice Hall, Englewood Cliffs (1994)Google Scholar
  50. 50.
    Yang, Y., Gopalakrishnan, G., Lindstrom, G., Slind, K.: Nemos: a framework for axiomatic and executable specifications of memory consistency models. In: IPDPS. IEEE (2004)Google Scholar
  51. 51.
    Zhang, N., Kusano, M., Wang, C.: Dynamic partial order reduction for relaxed memory models. In: PLDI, pp. 250–259. ACM (2015)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Parosh Aziz Abdulla
    • 1
    Email author
  • Mohamed Faouzi Atig
    • 1
  • Ahmed Bouajjani
    • 2
  • Tuan Phong Ngo
    • 1
  1. 1.Uppsala UniversityUppsalaSweden
  2. 2.IRIF Université Paris Diderot - Paris 7ParisFrance

Personalised recommendations