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Memory Circuits and Systems

  • Ahmet BindalEmail author
Chapter

Abstract

Basic serial and parallel bus structures and different forms of data transfer between a bus master and a slave were explained in Chap.  4. Regardless of the bus architecture, the bus master is defined as the logic block that initiates the data transfer while the slave is defined as the device that can only listen and exchange data with the master on demand.

Supplementary material

References

  1. 1.
    Toshiba datasheet TC59S6416/08/04BFT/BFTL-80, -10 Synchronous Dynamic RAMGoogle Scholar
  2. 2.
    Toshiba datasheet TC58DVM72A1FT00/TC58DVM72F1FT00 128Mbit E2PROMGoogle Scholar
  3. 3.
    Toshiba datasheet TC58256AFT 256Mbit E2PROMGoogle Scholar
  4. 4.
    Toshiba datasheet TC58FVT004/B004FT-85, -10, -12 4MBit CMOS Flash memoryGoogle Scholar
  5. 5.
    Toshiba datasheet TC58FVT400/B400F/FT-85, -10, -12 4MBit CMOS Flash memoryGoogle Scholar
  6. 6.
    Toshiba datasheet TC58FVT641/B641FT/XB-70, -10 64MBit CMOS Flash memoryGoogle Scholar
  7. 7.
    Atmel datasheet AT26DF161 16Mbit serial data Flash memoryGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Computer Engineering DepartmentSan Jose State UniversitySan JoseUSA

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