Design Automation for On-Chip Nanophotonic Integration

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Abstract

Recent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Significant developments in silicon photonic manufacturing and integration are enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology—and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles and boundaries of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this technology. Photonic design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications—thus fully realizing the potential of this technology.

This chapter describes our work on design automation for integrated optic system design. Using a building-block model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis. We also provide modeling for optical devices, and determine optimization and constraint parameters that guide the automation techniques. Starting from a logic design model, we describe how conventional logic synthesis and physical design techniques (placement, global and detail routing) can be applied in a top-down fashion to engineer a fully automated design flow for integrated optical systems.

Keywords

Ring Resonator Finite Difference Time Domain Integrate Optic Array Waveguide Grating Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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References

  1. 1.
     Soref R. The past, present, and future of silicon photonics. IEEE J Sel Top Quantum Electron. 2006;12:1678–87CrossRefGoogle Scholar
  2. 2.
    Condrat C, Kalla P, Blair S. Logic Synthesis for Integrated Optics. In: Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI, GLSVLSI ’11, New York:ACM; 2011. pp. 13–18.Google Scholar
  3. 3.
    Condrat C, Kalla P, Blair S. Exploring Design and Synthesis for Optical Digital Logic. International Workshop on Logic Synthesis, 2010.Google Scholar
  4. 4.
    Caulfield HJ, Vikram CS, Zavalin A. Optical logic redux. Optik. 2006;117:199–209CrossRefGoogle Scholar
  5. 5.
    Politi A, Matthews J, O’Brien J. “Shor’s Quantum Factoring Algorithm on a Photonic Chip. Science. 2009;325:1221CrossRefMATHMathSciNetGoogle Scholar
  6. 6.
    Hardy J, Shamir J. Optics Inspired Logic Architecture. Opt Express. 2007;15:150–65CrossRefGoogle Scholar
  7. 7.
    Caulfield et al. HJ. Generalized optical logic elements GOLEs. Opt Commun. 2007;271: 365–76Google Scholar
  8. 8.
    Ganapati P. Germanium laser breakthrough brings optical computing closer. Wired Mag. 2010Google Scholar
  9. 9.
    Blair S, Wagner K. Collision-based computing. Chapter gated logic with optical solitons. London: Springer, 2002. p. 355–80.Google Scholar
  10. 10.
    Shan A. Heterogeneous Processing: a Strategy for Augmenting Moore’s Law (http://www.linuxjournal.com/article/8368). Linux J. 2006; 142
  11. 11.
    Dokania Rk, Apsel AB. Analysis of challenges for on-chip optical interconnects. In: GLSVLSI, GLSVLSI. New York: ACM; 2009. pp. 275–80.Google Scholar
  12. 12.
    Batten C, Joshi A, Stojanovic V, Asanovic K, Designing chip-level nanophotonic interconnection networks. IEEE J Emerging Sel Top Circuits Syst. 2012;2:137–53CrossRefGoogle Scholar
  13. 13.
    Cianchetti M, Kerekes J, Albonesi D, Phastlane: A rapid transit optical routing network. In: Proceedings of the 36th annual International Symposium on Computer Architecture, ISCA ’09, New York:ACM; 2009. p. 441–450Google Scholar
  14. 14.
    Beausoleil et al. R. A nanophotonic interconnect for high-performance many-core computation. Symposium on High-Performance Interconnects, 2008. p. 182–189Google Scholar
  15. 15.
    Chan J, Hendry G, Bergman K, Carloni L. Physical-layer modeling and system-level design of chip-scale photonic interconnection networks. IEEE Trans Comput-Aided Design Integr Circuits Syst. 2011;30(10):1507–1520.CrossRefGoogle Scholar
  16. 16.
    Emelett SJ, Soref R. Design and simulation of silicon microring optical routing switches. J Lightwave Technol. 2005;23:1800CrossRefGoogle Scholar
  17. 17.
    Pearson et al. MR. Arrayed waveguide grating demultiplexers in silicon-on-insulator. In: Proceedings of SPIE, vol. 3953, 2000. p. 11–18Google Scholar
  18. 18.
    Boyd RW. Nonlinear optics, third edition. 3rd ed. Academic Press: New York; 2008.Google Scholar
  19. 19.
    Dinu M, Quochi F, Garcia H. Third-order nonlinearities in silicon at telecom wavelengths. Appl Phys Lett. 2003;82:2954–56CrossRefGoogle Scholar
  20. 20.
    Liao L et al. High speed silicon Mach-Zehnder modulator. Opt Express. 2005;13:3129–35CrossRefGoogle Scholar
  21. 21.
    Green W et al. Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator. Opt Express. 2007;15:17106–113CrossRefGoogle Scholar
  22. 22.
    Liao L, Liu A, Basak J, Nguyen H, Paniccia M, Rubin D, Chetrit Y, Cohen R, Izhaky N. Gbit/s silicon optical modulator for highspeed applications. Electron Lett. 2007;43(22):1196–1197CrossRefGoogle Scholar
  23. 23.
    Park H, Fang A, Kodama S, Bowers J. Hybrid silicon evanescent laser fabricated with a silicon waveguide and III-V offset quantum wells. Opt Express. 2005;13:9460–9464CrossRefGoogle Scholar
  24. 24.
    Lipson M. Compact electro-optic modulators on a silicon chip. IEEE J Sel Top Quantum Electron. 2006;12:1520–1526CrossRefGoogle Scholar
  25. 25.
    Gunn C, Masini GLI. Closing in on photonics large-scale integration. Photon Spectra. 2007Google Scholar
  26. 26.
    Miller DAB. Optical interconnects to electronic chips. Appl Opt. 2010;49:F59–F70CrossRefGoogle Scholar
  27. 27.
    Madsen C, Zhao J. Optical filter design and analysis: a signal processing approach. NewYork: Wiley, 1999.CrossRefGoogle Scholar
  28. 28.
    Condrat C, Kalla P, Blair S. A methodology for physical design automation for integrated optics. In: Proceedings of IEEE International Midwest Symposium on Circuits and Systems, 2012.Google Scholar
  29. 29.
    Condrat C, Kalla P, Blair S. Channel routing for integrated optics. In: Proceedings of ACM/IEEE System-Level Interconnect Prediction Workshop, 2013.Google Scholar
  30. 30.
    Condrat C, Kalla P, Blair S, Crossing-Aware Channel Routing for Photonic Waveguides. In: Proceedings of IEEE International Midwest Symposium on Circuits and Systems, 2013.Google Scholar
  31. 31.
    Condrat C, Kalla P, Blair S. Thermal-aware Synthesis of Integrated Photonic Ring Resonators. In: To appear in Proceeding of the International Conference on CAD (ICCAD), Nov. 2014.Google Scholar
  32. 32.
    Condrat C. Design Automation for Integrated Optics, PhD thesis, University of Utah, 2014.Google Scholar
  33. 33.
    Pollock C, Lipson M, Integrated photonics. Dordrecht:Kluwer Academic Publishers; 2003.Google Scholar
  34. 34.
    Koester SJ et al. Ge-on-SOI-detector/si-cmos-amplifier receivers for high-performance optical-communication applications. J Lightwave Technol. 2007;25:46–57CrossRefGoogle Scholar
  35. 35.
    OpSIS: Optoelectronic System Integration in Silicon. http://www.opsisfoundry.org.
  36. 36.
    Okamoto K. Fundamentals of optical waveguides. London: Academic Press; 2000.Google Scholar
  37. 37.
    Emelett S, Soref R. Analysis of dual-microring-resonator cross-connect switches and modulators. Opt Express. 2005;13:7840–53CrossRefGoogle Scholar
  38. 38.
    Shlager KL, Schneider JB. A Selective survey of the finite-difference time-domain literature. Advances in Computational electrodynamics: the finite-difference time-domain method. Boston:Artech House Inc; vol. 37, 1995. p. 39–56.Google Scholar
  39. 39.
    Bryant RE. Graph based algorithms for boolean function manipulation. IEEE Trans Comput. 1986;C-35:677–91CrossRefGoogle Scholar
  40. 40.
    Ding D, Pan D. Oil: a nano-photonics optical interconnect library for a new photonic network architecture. In: System-level interconnect prediction workshop (SLIP), 2009.Google Scholar
  41. 41.
    Ding D, Zhang Y, Huang H, Chen RT, Pan DZ. O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. In: Design Automation Conference 2009. p. 264–69.Google Scholar
  42. 42.
    Orcutt J, Ram R. Photonic device layout within the foundry cmos design environment. IEEE Photonics Technol Lett. 2010.Google Scholar
  43. 43.
    Ding D, Yu B, Pan D. “GLOW: a global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. In: 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 30 Jan–02 Feb 2012, p. 621–26.Google Scholar
  44. 44.
    Zheng Y, Lisherness P, Gao M, Bovington J, Cheng K, Wang H, Yang S. Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip. J Opt Commun Networking. 2012;4:955–66CrossRefGoogle Scholar
  45. 45.
    Bogaerts W, Dumon P, Thourhout DV, Baets R. Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides. Opt Lett. 2007;32:2801–03CrossRefGoogle Scholar
  46. 46.
    Sanchis P, Villalba P, Cuesta F, Håkansson A, Griol A, Galán JV, Brimont A, J. Martí J. Highly efficient crossing structure for silicon-on-insulator waveguides. Opt. Lett. 2009;34:2760–62.Google Scholar
  47. 47.
    Xu F, Poon AW, Silicon cross-connect filters using microring resonator coupled multimode-interference-based waveguide crossings. Opt. Express. 2008;16:8649–57.CrossRefGoogle Scholar
  48. 48.
    Cardenas J, Poitras CB, Robinson JT, Preston K, Chen L, Lipson M. Low loss etchless silicon photonic waveguides. Opt. Express. 2009;17:4752–57.CrossRefGoogle Scholar
  49. 49.
    Vlasov Y, McNab S. Losses in single-mode silicon-on-insulator strip waveguides and bends. Opt. Express. 2004;12:1622–31.CrossRefGoogle Scholar
  50. 50.
    Qian Y, Kim S, Song J, Nordin GP, Jiang J. Compact and low loss silicon-on-insulator rib waveguide 90∘ bend. Opt. Express. 2006;14:6020–28.CrossRefGoogle Scholar
  51. 51.
    Li G, Yao J, Thacker H, Mekis A, Zheng X, Shubin I, Luo Y, Lee J, Raj K, Cunningham JE, Krishnamoorthy AV. Ultralow-loss, high-density SOI optical waveguide routing for macrochip interconnects. Opt. Express. 2012;20:12035–39.CrossRefGoogle Scholar
  52. 52.
    Roy J, Papa D, Adya S, Chan H, Ng A, Lu J, Markov I. Capo: robust and scalable open-source min-cut floorplacer. In: Proceedings of the 2005 international symposium on Physical design, ISPD ’05. New York: ACM; 2005. p. 224–6.CrossRefGoogle Scholar
  53. 53.
    Larry M, Carl E. PathFinder: A Negotiation-based Performance-driven Router for FPGAs. In: Proceedings of the 1995 ACM Third International Symposium on Field-programmable Gate Arrays, FPGA ’95. New York: ACM; 1995. p. 111–7.Google Scholar
  54. 54.
    Pan M, Chu C. FastRoute 2.0: A High-quality and Efficient Global Router. In: Design Automation Conference, 2007. ASP-DAC ’07. Asia and South Pacific, 2007. p. 250–5.Google Scholar
  55. 55.
    Cho M, Lu K, Yuan K, Pan DZ. BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router, Ť ICCAD. In: In Proceeding of ICCAD 2007, 2007. pp. 503–8.Google Scholar
  56. 56.
    Chang Y, Lee Y, Wang T. NTHU-Route 2.0: A fast and stable global router. In: IEEE/ACM International Conference on Computer-Aided Design, 2008. ICCAD 2008. 2008. p. 338–43.Google Scholar
  57. 57.
    Hashimoto A, Stevens J. Wire routing by optimizing channel assignment within large apertures. In: Proceedings of the 8th Design Automation Workshop, DAC ’71. New York: ACM; 1971. p. 155–69.Google Scholar
  58. 58.
    Deutsch D. A dogleg channel router. In: Proceedings of the 13th Design Automation Conference, DAC ’76. New York:ACM; 1976. p. 425–33.Google Scholar
  59. 59.
    Yoshimura T, Kuh ES. Efficient algorithms for channel routing. IEEE Trans Comput Aided Des Integr Circuits Syst 1982;1:25–35.CrossRefGoogle Scholar
  60. 60.
    Condrat C, Kalla P, Blair S. Crossing-aware channel routing for integrated optics. IEEE Trans CAD, special section on optical interconnects 2014;33,6:814–25.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Christopher Condrat
    • 1
  • Priyank Kalla
    • 2
  • Steve Blair
    • 2
  1. 1.Calypto Design SystemsWilsonvilleUSA
  2. 2.Department of Electrical and Computer EngineeringUniversity of UtahSalt Lake CityUSA

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