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Optimization and Scaling of Micro-relays for Ultralow-Power Digital Logic

  • Hei Kam
  • Fred Chen
Chapter
Part of the Microsystems and Nanosystems book series (MICRONANO, volume 1)

Abstract

This chapter begins with general overview of the relay energy-delay optimization, followed by a sensitivity-based energy-delay optimization methodology. We establish simple relay design guidelines and examine the implications of scaling relay devices using the proposed design methodology. We also show that in a manner highly analogous to MOSFET scaling, dimensional scaling can be applied to relays to improve device density, switching delay, and power consumption.

Keywords

Beam Length Versus Norm Switching Delay Switching Energy Static Noise Margin 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Hei Kam
    • 1
  • Fred Chen
    • 2
  1. 1.Intel CorporationHillsboroUSA
  2. 2.Lion Semiconductor, Inc.BerkeleyUSA

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