Automatic Interface Generation among VHDL Processes in Hardware/Software Co-Design

Abstract

The modern electronic systems are becoming more complex, requiring shortest design time and demanding a decreasing in design cost. To achieve this, techniques for supporting hardware/software co-design have been developed in order to permit the joint specification, design and synthesis of mixed hardware/software systems. But the use of co-design brings to the designer a very hard and error prone task, the implementation of the interface between the hardware and software parts. This way the designer has to deal with three projects: the hardware, the software and the interface. The main goal of this work is the development of a methodology for automatic interface generation between concurrent processes, releasing the designer of this task and letting him or her free for spending efforts on the design of the system itself. This work focuses on the automatic interface generation between concurrent VHDL processes communicating through message passing. The proposed approach includes the development of a library of generic communication components, the definition of VHDL constructors for synchronous communication, as well as techniques for automatic VHDL code generation with synchronous communication, which can be simulated and synthesised by conventional CAD tools.