A General Model for Fault Covering Problems in Reconfigurable Arrays
An increase in chip density leads to a reduction in the yield of chip production. [Schu78] showed that in most cases, only a small number of elements in defective chips are actually defective. Thus the idea of repairing a chip after fabrication becomes very appealing. Reconfigurable chips are often used for this purpose. These chips contain redundant elements that can be used to repair the defective elements. There are many different ways to reconfigure a chip using redundant elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. In this paper we introduce a general model to represent the relationships between redundant elements and defective elements in a uniform way. This model generalizes the models discussed in previous approaches. We also give a complete characterization of the complexity of the fault covering problems for all the subcases of our model, most of which have not been studied before.
Unable to display preview. Download preview PDF.
- [Evan81]R. C. Evans, “Testing Repairable RAMs and Mostly Good Memories,” Proc. IEEE Int. Test Conference, pp. 49–55, 1981.Google Scholar
- [HaCL88a]N. Hasan, J. Cong and C. L. Liu, “A New Formulation for Fault Covering Problems in Reconfigurable Chips,” manuscript, 1988.Google Scholar
- [HaCL88b]N. Hasan, J. Cong and C. L. Liu, “A New Formulation of Yield Enhancement Problems for Reconfigurable Chips,” Proc. Intl. Conf. on Computer-Aided Design, pp. 520–523, Nov. 1988.Google Scholar
- [HaLi88]N. Ilasan and C. L. Liu, “Minimum Fault Coverage in Reconfigurable Arrays,” Proc. 18th Int. Symp. on Fault-Tolerant Computing, pp. 348–353, June 1988.Google Scholar
- [HoKa73]J. E. Hoperoft and R. M. Karp, “An n5/2 Algorithm for Maximum Matchings in Bipartite Graphs,” SIAM J. Comput., Vol. 2, No. 4., pp. 225–231, Dec. 1973.Google Scholar
- [Schu78]S. E. Schuster, “Multiple Word/Bit Line Redundancy for Semiconductor Memories,” IEEE J. Solid-State Circuits, Vol. SC-13, No. 5, pp. 698–703, Oct.1978.Google Scholar
- [Sing88]A. D. Singh, “Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays,” to appear in IEEE Trans. on Computers, Nov. 1988. Google Scholar
- [TaBo84]M. Tarr, D. Boudreau, and R. Murphy, “Defect Analysis System Speeds Test and Repair of Redundant Memories,” Electronics, pp. 175–179, Jan. 1984.Google Scholar
- [WeLo87]C. L. Wey and F. Lombardi, “On the Repair of Redundant RAM’s,” IEEE Trans. on Computer-Aided Design, Vol. Cad-6, No. 2, pp. 222–231, March 1987.Google Scholar