Formal semantics of VHDL timing constructs
Chapter
Abstract
The aim of the work presented here is to enlarge the subset of VHDL which can be manipulated by formal verification tools by including the timing constructs. In this paper we give formal semantics for these constructs. And, we prove, partially, the equivalence between these semantics and the informal operational semantics of the language as defined in the VHDL language reference manual. Also, we show how these semantics can establish a basis for the construction of formal timing verifiers.
Keywords
Semantic Model Operational Semantic Formal Semantic Physical Time Simulation Cycle
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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References
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© Springer Science+Business Media Dordrecht 1992