Fast Simulation of Computer Architectures pp 205-237 | Cite as
Performance Bounds for Rapid Computer System Evaluation
Chapter
Abstract
Simulation is generally used to model program execution characteristics under some set of conditions, for example the execution of a finite element application on a high speed workstation. The simulation output may include several performance metrics, such as the expected runtime, memory utilization, register usage, or processor cache performance.
Keywords
Performance Bound Clock Cycle Dependence Graph Instruction Schedule Vector Register
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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References
- [1]E. L. Boyd and E. S. Davidson. Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. In Proc. of the Int. Symp. on Computer Architecture, pages pp. 203–212, 1993.Google Scholar
- [2]CONVEX Architecture Reference (C200 Series). Technical Report 081-009330-000, Convex Computer Corporation, 1990.Google Scholar
- [3]CONVEX Theory of Operation (C200 Series). Technical Report 081-005030-000, Convex Computer Corporation, 1990.Google Scholar
- [4]An Introduction to the CRAY-1 Computer. Cray Research Inc., Chippewa Falls, WI, 1975.Google Scholar
- [5]The Cray-2 Computer System Functional Description. Cray Research Inc., Chippewa Falls, WI, July 1987.Google Scholar
- [6]Gerry Kane. Mips RISC Architecture. Prentice Hall, 1988.Google Scholar
- [7]William Mangione-Smith, Santosh G. Abraham, and Edward S. Davidson. Register Requirements of Pipelined Processors. In Proc. International Conference on Supercomputing, 1992.Google Scholar
- [8]William H. Mangione-Smith. Performance Bounds and Buffer Space Requirements for Concurrent Processors. PhD thesis, Univ. of Mich., EECS Dept., Univ. of Mich., Ann Arbor, MI, 1992.Google Scholar
- [9]William H. Mangione-Smith, Santosh G. Abraham, and Edward S. Davidson. The Effects of Memory Latency and Fine-Grain Parallelism on Astronautics ZS-1 Performance. In Proc. Twenty-Third Hawaii International Conference on System Sciences, pages 288–296, 1990.Google Scholar
- [10]William H. Mangione-Smith, Santosh G. Abraham, and Edward S. Davidson. A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. IEEE Computer, 24(1), January 1991.Google Scholar
- [11]William H. Mangione-Smith, Santosh G. Abraham, and Edward S. Davidson. Architectural vs. Delivered Performance of the IBM RS/6000 and the Astronautics ZS-1. In Proc. Twenty-Fourth Hawaii International Conference on System Sciences, January 1991.Google Scholar
- [12]William H. Mangione-Smith, Santosh G. Abraham, and Edward S. Davidson. Vector Register Design for Polycyclic Vector Scheduling. In Proc. Fourth Conference on Architectural Support for Programming Languages and Operating Systems, April 1991.Google Scholar
- [13]F. H. McMahon. The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range. Technical Report UCRL-53745, Lawrence Livermore National Laboratory, December 1986.Google Scholar
- [14]J. O. Murphy and R. M. Wade. The IBM 360/195. Datamation, April 1970.Google Scholar
- [15]R. R. Oehler and R. D. Groves. IBM RISC System/6000 Processor Architecture. IBM Journal of Research and Development, 34(1):23–36, January 1990.CrossRefGoogle Scholar
- [16]Janak H. Patel and Edward S. Davidson. Improving the Throughput of a Pipeline by Insertion of Delays. In Proc. of the Int. Symp. on Computer Architecture, pages 159–164, 1976.Google Scholar
- [17]R. M. Russell. The CRAY-1 Computer System. Communications of the ACM, 21(l):214–248, 1978.Google Scholar
- [18]B. J. Smith. A Pipelined Shared Resource MIMD Computer. In Proc. of the International Conference on Parallel Processing, 1978.Google Scholar
- [19]James E. Smith et al. The ZS-1 Central Processor. In Proc. of ASPLOS II, pages 199–204, October 1987.Google Scholar
- [20]Ju-Ho Tang. Performance Evaluation of Vector Machine Architectures. PhD thesis, CSRD, University of Illinois at Urbana-Champaign, 1989.Google Scholar
- [21]Ju-ho Tang and Edward S. Davidson. An Evaluation of Cray-1 and Cray X-MP Performance on Vectorizable Livermore Fortran Kernels. In Proc. of the 1988 International Conference on Supercomputing, pages 510–518, July 1988.Google Scholar
- [22]Ju-ho Tang, Edward S. Davidson, and Johau Tong. Polycyclic Vector Scheduling vs. Chaining on 1-Port Vector Supercomputers. In Proc. of Supercomputing’ 88, pages 122–129, 1988.Google Scholar
- [23]Daniel Windheiser and William Jalby. Behavioral Characterization of Decoupled Access/Execute Architectures. In 1991 ACM International Conference on Supercomputing, 1991.Google Scholar
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