Bit-Level Unfolding

Abstract

In chapter 7 a technique of word-level unfolding was described in which a single computational stream is unfolded into several computational streams carrying out the same computation independently or in an interleaved manner. In this chapter we describe a technique investigated by Parhi ([10][9]) called “bit-level unfolding”. This method gives a systematic way of generating digit-serial designs from bit-serial designs. The method does not make fundamental use of the fact that the original design is a “bit-serial design”, but can be applied to any synchronous design made up of combinational circuitry and delay latches. We make the assumption only that the circuit should be synchronous, that is, there are no unclocked feedback loops.