Transmission Gate Modeling

Jeong-Taek Kong; David Overhauser

doi:10.1007/978-1-4615-2321-5_6

Digital Timing Macromodeling for VLSI Design Verification pp 191-198 | Cite as

Transmission Gate Modeling

Authors
Authors and affiliations

Jeong-Taek Kong
David Overhauser

Chapter

52 Downloads

Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 319)

Abstract

In this chapter, a gate driving a transmission gate and fanout gates is modeled. The effective resistance of the transmission gate is obtained as a function of the input slope of the driver. The methods applied to model the RC-interconnect effects are extended to model the gate driving transmission gates.

This is a preview of subscription content, to check access.

Preview

Unable to display preview. Download preview PDF.

Copyright information

Authors and Affiliations

Jeong-Taek Kong
- 1
David Overhauser
- 2

1.Samsung Electronics Co., Ltd.Korea
2.Duke UniversityUSA

About this chapter

Cite this chapter as:: Kong JT., Overhauser D. (1995) Transmission Gate Modeling. In: Digital Timing Macromodeling for VLSI Design Verification. The Springer International Series in Engineering and Computer Science (VLSI, Computer Architecture and Digital Signal Processing), vol 319. Springer, Boston, MA

DOI https://doi.org/10.1007/978-1-4615-2321-5_6
Publisher Name Springer, Boston, MA
Print ISBN 978-1-4613-5982-1
Online ISBN 978-1-4615-2321-5
eBook Packages Springer Book Archive

Personalised recommendations

Actions

Buy eBook

USD 169.00

Instant download
Readable on all devices
Own it forever
Local sales tax included if applicable