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A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines

  • Egon Börger
  • Uwe Glässer
  • Wolfgang Muller
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 307)

Abstract

We present a rigorous but transparent semantic definition for VHDL corresponding to the IEEE VHDL’ 93 standard [68, 9, 84]. Our definition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our specification defines an abstract VHDL ’ 93 interpreter in the form of transition rules for an evolving algebra machine (EA-Machine) [60]. It faithfully reflects and supports the view of simulation given in the IEEE VHDL ’ 93 standard language reference manual. The definition can be understood without any prior formal training. We illustrate our definition by running the example VHDL program set out in the Introduction to this volume.

Keywords

Transition Rule Formal Verification Variable Assignment Kernel Process Simulation Cycle 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1995

Authors and Affiliations

  • Egon Börger
    • 1
  • Uwe Glässer
    • 2
  • Wolfgang Muller
    • 3
  1. 1.Dipartimento di InformaticaUniversità di PisaItaly
  2. 2.Heinz Nixdorf InstitutUniversität-GH PaderbornGermany
  3. 3.CadlabUniversität-GH PaderbornGermany

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