Optimization of Synchronous Circuits

  • Soha Hassoun
  • Tiziano Villa
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 654)

Abstract

We study techniques for optimizing synchronous sequential circuits. These techniques use either state-based or structural gate-level models. We survey recent advances in state-based techniques focusing on the computation of the flexibility in synthesizing or resynthesizing a node in a network of Finite State Machines. We then survey structural sequential optimization techniques that either relocate registers within the circuit (retiming) or that modify both register placement and the circuit’s combinational logic.

Keywords

Finite State Machine Clock Period Sequential Circuit Logic Synthesis Logic Optimization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Soha Hassoun
  • Tiziano Villa

There are no affiliations available

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