SOPC Builder: Performance By Design

Abstract

We are now in the era of programmable logic. The need for low-cost, high-performance methods of getting to market in the shortest amount of time are ever present. This requires tools and methodologies that leverage the strengths of the designers, utilize known-to-work components, and allow rapid experimentation and innovation. Altera’s SOPC Builder is this tool. SOPC Builder is used to construct embedded “Systems on a Programmable Chip” (SOPC) from a wide variety of components that are available natively (the Nios soft-core microprocessor, communications IP, memory interfaces, timers, etc.) or from 3rd party IP providers. Additionally it is a framework into which developers can place their own custom IP cores for easy reuse. The power of this tool and design methodology lies in the fact that it abstracts away the tedious tasks, such as developing the bus wiring, arbitration logic, and memory map decode, and allows the designer to spend more time on architectural issues, such as system performance or software/hardware co-design. With SOPC Builder the designer is able to iterate through designs quickly, testing which one will provide the most optimal performance for the given problem, testing things like simultaneous multi-master architectures, multi-processors, and where to make the split between software algorithms and hardware acceleration. Working systems are generated in minutes, and architectural evolution can begin immediately, giving faster time-to-market and providing a perfectly tailored solution in the end.