Formal Verifications of Systems on Chips: Current and Future Directions

  • Khaled M. Elleithy
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 711)


In this tutorial we present the area of formal verification of systems on Chips. The paper discuses the following topics: different approaches of formal logic such as first order bgic, high order logic, temporal logic. A case study of object-oriented paradigm is presented. A survey of the current research status is presented. The paper concludes with a section on the future directions.


Formal verification first order logic high order logic temporal logic automated theorem provers object oriented paradigm 


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  1. 1.
    Elleithy, K. M. “Formal Hardware Verification of VLSI Architecture Current Status and Future Directions,” Fifth International Conference on Microelectronics, Dhahran, pp. 197–201, Dec. 1993.Google Scholar
  2. 2.
    Uehara, T., et al., “DDL Verifier and Temporal Logic,” Proc. CHDL 83: IFIP 6th Int’l Symp. Computer Hardware Description Languages and their Applications, Pittsburgh, May 1983, pp. 91.Google Scholar
  3. 3.
    Dieter Fensel, Jürgen Angele, and Rudi Studer, “The Knowledge Acquisition and Representation, KARL,” IEEE Transactions and on Knowledge and Data Engineering, July-August 1998, pp. 527–550.Google Scholar
  4. 4.
    Hunt, W. A., “FM8501: A verified Microprocessor,” IFIP WG 10.2 Workshop, From HDL Descriptions to Guaranteed Correct Circuits Design, North Holland Publishing, Amsterdam, Sept. 1986, pp. 85–114.Google Scholar
  5. 5.
    Hanna, F. K. and Daeche, “Specification and Verification of Digital Systems Using Higher order Logic,” IEE proc., Vol. 133, Pt. E, No. 5, Sept. 1986, pp. 242–254.Google Scholar
  6. 6.
    Brackin, S.H., “A HOL extension of GNY for automatically analyzing cryptographic protocols,” Proceedings of the Ninth IEEE Computer Security Foundations Workshop, 1996.Google Scholar
  7. 7.
    Phillip J. Windley, “Formal Modeling and Verification of Microprocessors,” IEEE Transactions on Computers, 1995 IEEE Vol. 44, No. 1; January 1995, pp. 54–72.zbMATHCrossRefGoogle Scholar
  8. 8.
    Joyce, J., “Formal Verification and Implementation of a Microprocessor,” VLSI Specification, Verification, and Synthesis, Birtwistle, G. and Subrahmanyam, P.A., eds., North Holland, Amsterdam, The Netherlands, 1988, pp. 371–378.Google Scholar
  9. 9.
    Bochmann, G. V., “Hardware Specification with Temporal Logic: An Example,” IEEE Trans. Computers, Mar. 1982, pp. 223–231.Google Scholar
  10. 10.
    Fujita, M., et al., “Logic Design Assistance with Temporal Logic,” Proc. CHDL 85: IFIP 7th Int’l Symp. Computer Hardware Description Languages and their Applications, Aug. 1985, pp. 129–137.Google Scholar
  11. 11.
    Elleithy, K. M. and Aref, M., “A Production Based System for Formal Verification of Digital Signal Processing Architectures,” Twenty-Seventh Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, pp. 1618–1622, Nov. 1–3, 1993.Google Scholar
  12. 12.
    Nebel, W. and Schumacher, G., “Object-Oriented Hardware Modelling — Where to Apply and what are the objects?,” Proc. of the Euro-Dac 1996 with Euro-VHDL 96, IEEE Computer Society Press 1996.Google Scholar
  13. 13.
    Glunz, W., et al., “System Level Synthesis, “in Michel, P. and et al. (eds): The Synthesis Approach to Digital System Design, Kluwer, pp. 221–260, 1992.Google Scholar
  14. 14.
    Zippelius, R. et al. “An Object Oriented Extension to VHDL,” Proceedings of the VHDL-Forum, Spring ′92 Meeting, 1992.Google Scholar
  15. 15.
    Willis, J., et al.”A Proposal for Minimally Extending VHDL to Achieve Data Encapsulation and Multiple Inheritance,” Proceedings of the VHDL International User’s Forum, 1994.Google Scholar
  16. 16.
    Schumacher, G. and Nebel, W., “Inheritance Concept For Signals in Object-Oriented Extensions to VHDL,” Proc. of the Euro-Dac 1995 with Euro-VHDL 95, IEEE Computer Society Press 1995.Google Scholar
  17. 17.
    Shostak, R. E., “Formal Verification of Circuit Designs,” Proc. CHDL ′83: IFIP 6th Int’l Symp. Computer Hardware Description Languages and their Applications, Pittsburgh, May 1983, pp. 13–30.Google Scholar
  18. 18.
    Clarke, E. M., Long, D. E., McMillan, K. L., “A Language for Compositional Specification and Verification of Finite State Hardware Controllers,” Proc. Nith Symp. on Computer Hardware Description Languages and their Applications, Darringer, J. A. and Rammig, F. J., eds., North Holland, Amsterdam, The Netherlands, 1989, Participants Edition, pp. 281–295.Google Scholar
  19. 19.
    Moszkowski, B., “A Temporal Logic for Multilevel Reasoning about Hardware,” Computer, Feb. 1985, pp. 10–19.Google Scholar
  20. 20.
    Moszkowski, B., Executing Temporal Logic Programs, Cambridge University Press, Cambridge, England, 1986.Google Scholar
  21. 21.
    Boyer, R. S. and Moore, J. S., A Computational Logic Handbook, Academic Press, San Diego, Cali, 1988.zbMATHGoogle Scholar
  22. 22.
    Cohn, A., “A Proof of Correctness of the Viper Microprocessor: The First Level,” VLSI Specification, Verification and Synthesis, Birtwistle, G. and Subrahmanyam, P.A., eds., North Holland, Amsterdam, The Netherlands, 1988, pp. 27–71.Google Scholar
  23. 23.
    German S. M. and Wang Y., “Formal Verification of Parameterized Hardware Designs,” Proc. of the Int’l Conf. on Computer Design: VLSI in Computers, 1985, pp. 549–522.Google Scholar
  24. 24.
    Chandrasekhar, M. S., Privitera, J. P. and Conradt., K. W., “Application of Term Rewriting Techniques to Hardware design Verification,” Proc. of the 24th Design Automation Conference, IEEE Computer Society Press, Los Alamos, Cali, 1987, pp. 27–71.Google Scholar

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© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Khaled M. Elleithy
    • 1
  1. 1.Department of Computer Science and EngineeringUniversity of BridgeportBridgeportUSA

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