System-on-a-Chip Design

  • Roopak Sinha
  • Parthasarathi Roop
  • Samik Basu
Chapter
First Online:

Abstract

A rapid surge in the consumer electronics revolution of the past decade may be attributed to the advancement in automated design techniques for system-on-chips (SoCs). SoCs are designed by reusing many different intellectual property (IP) blocks, that are integrated using a common platform, such as a set of standard buses from a given vendor, like ARM. While there have been considerable progress of SoC design techniques such as platform-based design and the reuse methodology manual-based design, system-level verification still poses considerable challenges. For example, it has been a widely accepted fact that the system-level verification phase often consumes about 50–80% of the overall design effort. This problem is exacerbated in safety-critical systems such as medical devices. This chapter develops a correct-by-construction design flow for SoCs. This is achieved by augmenting existing design flows with a systematic approach to system-level verification. We motivate this design-flow using a mobile phone SoC example and also outline how this design-flow is presented in the rest of this book.

Keywords

Intellectual Property Model Check Design Flow Universal Mobile Telecommunication System Universal Mobile Telecommunication System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Roopak Sinha
    • 1
  • Parthasarathi Roop
    • 1
  • Samik Basu
    • 2
  1. 1.Electrical and Computer EngineeringThe University of AucklandAucklandNew Zealand
  2. 2.Department of Computer ScienceIowa State UniversityAmesUSA

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