Design of Neuromorphic Architectures with Memristors

  • Dhireesha Kudithipudi
  • Cory Merkel
  • Mike Soltiz
  • Garrett S. Rose
  • Robinson E. Pino
Part of the Advances in Information Security book series (ADIS, volume 55)


Next-generation high-performance computing processors have a pressing need to expand their computation capabilities to support massively parallel applications. Moreover, conventional Von Neumann based architectures cannot meet these complex computational demands. Neuromorphic architectures, which improve the efficiency and robustness of complex computations by emulating the behavior of biological processes in hardware, offer a viable alternative solution. In this chapter, we discuss the design criteria and challenges to realize such architectures using emerging memristor technology. In particular, the memristor models, synapse circuits, fundamental processing units (neural logic blocks) for the neuromorphic architectures, and hybrid CMOS/memristor neural network (CMHNN) topologies using supervised learning will be presented for different benchmarks.


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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Dhireesha Kudithipudi
    • 1
  • Cory Merkel
    • 1
  • Mike Soltiz
    • 1
  • Garrett S. Rose
    • 2
  • Robinson E. Pino
    • 3
  1. 1.NanoComputing Research Lab, Department of Computer EngineeringRochester Institute of TechnologyRochesterUSA
  2. 2.Information Directorate, Air Force Research LaboratoryRomeUSA
  3. 3.ICF InternationalBaltimoreUSA

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