Bio-Inspired Online Fault Detection in NoC Interconnect



Technology scaling over the years has enabled the integration of multiple processing cores on a single chip with Network-on-chip (NoC) becoming an interconnect standard for facilitating large scale connectivity between cores. However, these NoC components, like any other circuit components, are also becoming more susceptible to faults with further scaling. The ability to adapt and perform reliably in the presence of these faults is an emerging design challenge for NoC-based multiprocessor systems. A crucial requirement for such designs is to effectively detect the faults during runtime, in particular with the ability to differentiate between temporary and permanent faults. Developing interconnect architectures with online, low-cost fault detection capabilities remains largely unaddressed and is a major design challenge for current and future scalable NoC-based multiprocessor systems. This chapter introduces SMART, a novel “real-time” strategy for detecting faults in NoC interconnect by using biological synapses and neurons to detect temporal and spatial faults. Analysis of fault scenarios and results from real-time experiments on an FPGA implementation of SMART using the example EMBRACE NoC are provided.


Fault Detection Inhibitory Synapse Flip Flop Cyclic Redundancy Check Permanent Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Intelligent Systems Research CentreUniversity of UlsterDerryUK

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