Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework

  • Kim Grüttner
  • Kai Hylla
  • Sven Rosinger
  • Wolfgang Nebel
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 106)


Consideration of an embedded system’s timing behaviour and power consumption at system-level is increasingly important nowadays but it is also an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made.In this paper we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SWsystems. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C\(++\) specification. These prototypes are enriched by static and dynamic power values as well as execution times. This efficient code annotation technique enables a fast host simulation and allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow will be implemented in the COMPLEXFP7 European integrated project.


Power Dissipation Basic Block Virtual Prototype Leakage Power Virtual Platform 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Benini, L., Hodgson, R., Siegel, P.: System-Level Power Estimation and Optimization. In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, pp. 173–178. ACM, New York, NY, USA (1998). DOI 10.1145/280756.280881Google Scholar
  2. 2.
    Densmore, D., Passerone, R., Sangiovanni-Vincentelli, A.: A Platform-Based Taxonomy for ESL Design. IEEE Design and Test of Computers 23(5), 359–374 (2006).
  3. 3.
    Grüttner, K., Andreas, H., Hartmann, P.A., Schallenberg, A., Brunzema, C.: OSSS – A Library for Synthesisable System Level Models in SystemC TM (2008).
  4. 4.
    Grüttner, K., Grabbe, C., Oppenheimer, F., Nebel, W.: Object Oriented Design and Synthesis of Communication in Hardware-/Software Systems with OSSS. In: Proceedings of the SASIMI 2007 (2007)Google Scholar
  5. 5.
    Helms, D., Ehmen, G., Nebel, W.: Analysis and Modeling of Subthreshold Leakage of RT-Components Under PTV and State Variation. Proceedings on International Symposium on Low Power Electronics and Design (2006)Google Scholar
  6. 6.
    Kruse, L., Schmidt, E., Jochens, G., Stammermann, A., Nebel, W.: Low Power Binding Heuristics. Proceedings on Int’l Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS pp. 41–50 (1999)Google Scholar
  7. 7.
    Macii, E., Pedram, M., Somenzi, F.: High-Level Power Modeling, Estimation, and Optimization. IEEE Trans. On Computer Aided Design 17, 1061–1079 (1998)CrossRefGoogle Scholar
  8. 8.
    Paulin, P., Knight, J.: Force-Directed Scheduling for the Behavioral Synthesis of ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, 661–679 (1989)CrossRefGoogle Scholar
  9. 9.
    Rabaey, J.M., Burke, D., Lutz, K., Wawrzynek, J.: Workloads of the Future. IEEE Design an Test of Computers 25(4), 358–365 (2008).
  10. 10.
    Renau, J., Fraguela, B., Tuck, J., Liu, W., Prvulovic, M., Ceze, L., Sarangi, S., Sack, P., Strauss, K., Montesinos, P.: SESC Simulator (2005). Http://
  11. 11.
    Sangiovanni-Vincentelli, A.: Quo Vadis SLD: Reasoning about Trends and Challenges of System-Level Design. Proceedings of the IEEE 95(3), 467–506 (2007)CrossRefGoogle Scholar
  12. 12.
    Sangiovanni-Vincentelli, A.: Is a Unified Methodology for System-Level Design Possible? IEEE Design and Test of Computers 25(4), 346–357 (2008).
  13. 13.
    Sangiovanni-Vincentelli, A., Martin, G.: Platform-Based Design and Software Design Methodology for Embedded Systems. IEEE Design and Test of Computers 18(6), 23–33 (2001).
  14. 14.
    The COMPLEX project (247999): COdesign and Power Management in PLatform-based design space EXploration (COMPLEX).
  15. 15.
    Vanderperren, Y., Dehaene, W.: A Model Driven Development Process for Low Power SoC Using UML. Springer (2005)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Kim Grüttner
    • 1
  • Kai Hylla
    • 2
  • Sven Rosinger
    • 2
  • Wolfgang Nebel
    • 3
  1. 1.Hardware-/Software Design Methodology Group, OFFIS – Institute for Information TechnologyOldenburgGermany
  2. 2.Analysis of Nanoelectronic Integrated Circuits, OFFIS – Institute for Information TechnologyOldenburgGermany
  3. 3.Faculty II – Department for Computer ScienceCarl von Ossietzky UniversityOldenburgGermany

Personalised recommendations