Embedded Systems Start-Up Under Timing Constraints on Modern FPGAs

  • Joachim MeyerEmail author
  • Juanjo Noguera
  • Michael Hübner
  • Rodney Stewart
  • Jürgen Becker


In this chapter the authors present advanced techniques, methods, and tool flows that enable embedded systems implemented on FPGAs to start up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the start-up time of the embedded software. Thereby the start-up time for timing-critical parts of a design is neither dependent on the complexity of the complete system nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.


Field Programmable Gate Array (FPGA) Modern FPGAs FPGA Configuration Dynamic Partial Reconfiguration Partial Bitstream 
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Copyright information

© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  • Joachim Meyer
    • 1
    Email author
  • Juanjo Noguera
    • 2
  • Michael Hübner
    • 1
  • Rodney Stewart
    • 3
  • Jürgen Becker
    • 1
  1. 1.Karlsruhe Institute of TechnologyKarlsruheGermany
  2. 2.Xilinx Inc.DublinIreland
  3. 3.Xilinx Inc.KillarneyIreland

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