Chapter

Reconfigurable Computing

pp 239-259

Date:

ERA – Embedded Reconfigurable Architectures

  • Stephan WongAffiliated withTechnische Universiteit Delft
  • , Luigi CarroAffiliated withUniversidade do Rio Grande do Sul Email author 
  • , Mateus RutzigAffiliated withUniversidade do Rio Grande do Sul
  • , Debora Motta MatosAffiliated withUniversidade do Rio Grande do Sul
  • , Roberto GiorgiAffiliated withUniversita’ degli Studi di Siena
  • , Nikola PuzovicAffiliated withUniversita’ degli Studi di Siena
  • , Stefanos KaxirasAffiliated withIndustrial Systems Institute
  • , Marcelo CintraAffiliated withUniversity of Edinburgh
  • , Giuseppe DesoliAffiliated withST Microelectronics
    • , Paolo GaiAffiliated withEvidence
    • , Sally A. MckeeAffiliated withChalmers University
    • , Ayal ZaksAffiliated withIBM

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Abstract

In a scenario where the complexity and diversity of embedded systems is rising and causing extra pressure in the demand for performance at the lowest ­possible power budget, designers face the challenge brought by the power and memory walls in the production of embedded platforms. The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through these walls, and help design the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of ­varying computing elements, networking elements, and memory elements. For computing elements, ERA utilizes a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores. These are dynamically adapted regarding their composition, organization, and even instruction-set architectures, to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler, exploiting the synergism between software and hardware. Having the complete freedom to flexibly tune the hardware elements allows for a much higher level of efficiency, riding the trade-off curve between ­performance and power compared to the state of the art. An additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.