ERA – Embedded Reconfigurable Architectures

  • Stephan Wong
  • Luigi Carro
  • Mateus Rutzig
  • Debora Motta Matos
  • Roberto Giorgi
  • Nikola Puzovic
  • Stefanos Kaxiras
  • Marcelo Cintra
  • Giuseppe Desoli
  • Paolo Gai
  • Sally A. Mckee
  • Ayal Zaks


In a scenario where the complexity and diversity of embedded systems is rising and causing extra pressure in the demand for performance at the lowest ­possible power budget, designers face the challenge brought by the power and memory walls in the production of embedded platforms. The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through these walls, and help design the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of ­varying computing elements, networking elements, and memory elements. For computing elements, ERA utilizes a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores. These are dynamically adapted regarding their composition, organization, and even instruction-set architectures, to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler, exploiting the synergism between software and hardware. Having the complete freedom to flexibly tune the hardware elements allows for a much higher level of efficiency, riding the trade-off curve between ­performance and power compared to the state of the art. An additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.


Embed System Power Budget Memory Hierarchy Embed Processor Reconfigurable Hardware 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



We would like to acknowledge the Valorisation Centre in Delft, and in particular two persons: Linda Roos and Theresia Twickler. They are responsible for the (financial) management of the project and their contributions/efforts allowed all the researchers involved in the ERA project to properly focus on their research tasks.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Stephan Wong
    • 1
  • Luigi Carro
    • 2
  • Mateus Rutzig
    • 2
  • Debora Motta Matos
    • 2
  • Roberto Giorgi
    • 3
  • Nikola Puzovic
    • 3
  • Stefanos Kaxiras
    • 4
  • Marcelo Cintra
    • 5
  • Giuseppe Desoli
    • 6
  • Paolo Gai
    • 7
  • Sally A. Mckee
    • 8
  • Ayal Zaks
    • 9
  1. 1.Technische Universiteit DelftDelftThe Netherlands
  2. 2.Universidade do Rio Grande do SulPasso FundoBrazil
  3. 3.Universita’ degli Studi di SienaSienaItaly
  4. 4.Industrial Systems InstitutePatrasGreece
  5. 5.University of EdinburghEdinburghUK
  6. 6.ST MicroelectronicsAgrate BrianzaItaly
  7. 7.EvidenceEdinburghItaly
  8. 8.Chalmers UniversityGothenburgSweden
  9. 9.IBMHaifaIsrael

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