Interconnect Issues

  • Stuart K. Tewksbury
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 70)

Abstract

This chapter reviews several system performance limits imposed on electronic digital systems by their electrical interconnection fabric. Relaxing such limits is perhaps the major motivation for WSI, though different WSI projects typically address different interconnection issues.

Keywords

Line Length Very Large Scale Integrate Transmission Line Model Switching Energy Line Capacitance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    T. Li, Advances in optical fiber communications: A historical perspective, IEEE J. Sel. Areas Commun., vol. SAC-1, pp. 356–372 (1983).Google Scholar
  2. [2]
    W.J. Goodman, F.J. Leonberger, S.Y. Kung and R.A. Athale, Optical interconnections for VLSI systems, Proc. IEEE, vol. 72, pp. 850–866 (1984).CrossRefGoogle Scholar
  3. [3]
    A. Husain, Optical interconnect of digital integrated circuits and systems, Proc. SPIE, vol. 466: Optical Interfaces for Digital Circuits and Systems, pp. 10–20 (1985).Google Scholar
  4. [4]
    J. D. Harris and H. E. T. Connell, An interconnection scheme for a tightly coupled massively parallel computer network, Proc. Int. Conf. Computer Design, pp. 612–616 (1985).Google Scholar
  5. [5]
    D. L. Carter and D. F. Guise, Effects of interconnects on submicron chip performance, VLSI Design, pp. 63–68 (Jan 1984).Google Scholar
  6. [6]
    E. T. Lewis, Optimization of device area and overall delay for CMOS VLSI designs, Proc. IEEE, vol. 72, pp. 670–689 (1984).CrossRefGoogle Scholar
  7. [7]
    D. B. Scott, W. R. Hunter and H. Shichijo, A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits, IEEE J. Solid-State Circuits, vol. SC-17, pp. 281–291 (1982).CrossRefGoogle Scholar
  8. [8]
    R. J. Antinone and G. W. Brown, The modeling of resistive interconnects for integrated circuits, IEEE J. Solid-State Circuits, vol. SC-18, pp. 200–203 (1983).CrossRefGoogle Scholar
  9. [9]
    W. E. Donath, Placement and average interconnection lengths of computer logic, IEEE Trans. Circuits and Syst., vol. CAS-26, pp. 272–277 (1979).CrossRefGoogle Scholar
  10. [10]
    L. Snyder, Introduction to the configurable, highly parallel computer, IEEE Computer, pp. 47–57 (Jan 1982).Google Scholar
  11. [11]
    R. Cohen, J. F. McDonald, M. Sanya and J. W. Woods, A wafer scale integration video rate fully recursive two-dimensional filter, Proc. IEEE Int. Conf. Computer Design, pp. 234–239 (1985).Google Scholar
  12. [12]
    C. Val, Wafer scale integration (WSI) packaging, in Wafer Scale Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Pub., pp. 321–344 (1986).Google Scholar
  13. [13]
    E. T. Lewis, The VLSI package – an analytic review, IEEE Trans Comp. Hybr., Manuf. Technol., vol. CHMT-7, pp 197–201 (1984).CrossRefGoogle Scholar
  14. [14]
    P. M. B. Vitanyi, Area penalty for sublinear signal propagation delay on chip, Proc. 26th Symp. Foundations of Computer Science, pp. 197–207 (1985).Google Scholar
  15. [15]
    G. Bilardi, M. Pracchi and F. P. Preparata, A critique and an appraisal of VLSI models of computation, in VLSI Systems and Computations, H. T. Rung, B. Sproull and G. Steel (Eds), Springer Verlag, Berlin, pp. 81–88 (1981).Google Scholar
  16. [16]
    D. Baker, D. C. Koehler, W. O. Fleckenstein, C. E. Roden and R. Sabia, Physical Design of Electronic Systems: Vol.1 Design Technology, Prentice-Hall (N.J.), 1970. Chapter 9.Google Scholar
  17. [17]
    R. W. Keyes, Fundamental limits in digital information processing, Proc. IEEE, vol. 69, pp. 267–278 (1981).CrossRefGoogle Scholar
  18. [18]
    T. C. Edwards, Foundations for Microstrip Circuit Design, John Wiley & Sons, New York (1981).Google Scholar
  19. [19]
    K. C. Gupta, R. Garg and I. J. Bahl, Microstrip Lines and Slotlines, Artech House, Dedham, MA (1979).Google Scholar
  20. [20]
    S. K. Tewksbury, L. A. Hornak and M. Hatamian, High-T c superconductors for digital system interconnections. in Superconductivity: Theory and Applications, Elsevier, New York (1988).Google Scholar
  21. [21]
    T. Sakurai, Approximation of wiring delay in MOS LSI, IEEE J. Solid-State Circuits, vol. SC-18, pp. 418–425 (1983).CrossRefGoogle Scholar
  22. [22]
    H-T. Yuan, Y-T. Lin and S-Y. Chiang, Properties of interconnection on silicon, sapphire and semi-insulating gallium arsenide substrates, IEEE J. Solid-State Circuits, vol. SC-17, pp. 269–274 (1982).CrossRefGoogle Scholar
  23. [23]
    M. J. Elmansry, Interconnect delays in MOSFET VLSI, IEEE J. Solid-State Circuits, vol. SC-16, pp. 585–591 (1981).CrossRefGoogle Scholar
  24. [24]
    G. Bilardi, M. Pracchi and F. P. Preparata, A critique of network speed in VLSI models of computation, IEEE J. Solid-State Circuits, vol. SC-17, pp. 696–702 (1982).CrossRefGoogle Scholar
  25. [25]
    A. Masaki and T. Chiba, Design aspects of VLSI for computer logic, IEEE Trans Elect. Dev., vol. ED-29, pp. 751–755 (1982).CrossRefGoogle Scholar
  26. [26]
    S. K. Tewksbury, Attojoule MOSFET logic devices using low voltage swings and low temperature, Solid-State Electronics, vol. 28, pp. 255–276 (1985).CrossRefGoogle Scholar
  27. [27]
    H. Hasegawa, M. Furukawa and H. Yanai, Properties of microstrip lines on Si - SiO2 system, IEEE Trans. Microwave Theory Tech., vol. MTT-19, pp. 869–881 (1971).CrossRefGoogle Scholar
  28. [28]
    H. Hasegawa and S. Seki, Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS microstrip line model, IEEE Trans. Elect. Dev., vol. ED-31, pp. 1954–1960 (1984).CrossRefGoogle Scholar
  29. [29]
    M. Robinson, D.J. Lischner and G.K. Celler, Large area recrystallization of polysilicon with tungsten-halogen lamps, J. Crystal Growth, vol. 63, pp. 484–492 (1983).CrossRefGoogle Scholar
  30. [30]
    W. H. Chang, Analytic IG metal-line capacitance formulas, IEEE Trans. Microwave Theory and Techniques, vol. MMT-24, pp. 608–611 (1976). Also, vol. MMT-25, pg. 712 (1977).CrossRefGoogle Scholar
  31. [31]
    C. P. Yuan and T. N. Trick, A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits, IEEE Elect. Dev. Lett., vol. EDL-3, pp. 391–393 (1982).CrossRefGoogle Scholar
  32. [32]
    A. J. Blodgett and D. R. Barbour, Thermal conduction module: A high performance multilayer ceramic package, IBM J. Res. Develop., vol 26, pp. 30–36 (1982).CrossRefGoogle Scholar
  33. [33]
    R. K. Spielberger, C. D. Huang, W. H. Nunne, A. H. Mones, D. L. Fett, and F. L. Hampton, Silicon-on-silicon packaging, IEEE Trans Compon., Hybr., Manuf. Technol., vol. CHMT-7, pp. 193–196 (1984).CrossRefGoogle Scholar
  34. [34]
    A. V. Brown, An overview of Josephson packaging, IBM J. Res. Develop., vol 24, pp. 167–171 (1980).CrossRefGoogle Scholar
  35. [35]
    T. Oseth, S. Yalamanchili, D. Lee and C. Sullivan, Impact of optical interconnects on VLSI architectures, Proc. NAECOM Conf., pp. 32–38 (1987).Google Scholar
  36. [36]
    R.H. Dennard, F.H. Gaennslen, H-N. Yu, V.L. Rideout, E. Bassous and A. R. LeBlanc, Design of ion-implanted MOSFET’s with very small dimensions, IEEE J. Solid-State Circ, vol. SC-9, pp. 256–268 (1974).CrossRefGoogle Scholar
  37. [37]
    J. R. Brews, W. Fichtner, E. H. Nicollian and S. M. Sze, Generalized guide for MOSFET miniaturization, IEEE Elect. Dev. Lett., vol. EDL-1, pp. 2–4 (1980).CrossRefGoogle Scholar
  38. [38]
    T. Toyabe and S. Asai, Analytic models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis, IEEE Trans. Elect. Dev., vol ED-26, pp. 453–461 (1979).CrossRefGoogle Scholar
  39. [39]
    G. Baccarani, M. R. Wordeman and R. H. Dennard, Generalized scaling theory and its application to a 1/4 micron MOSFET design, IEEE Trans. Electron Devices, vol. ED-29, pp. 1660–1661 (1982).CrossRefGoogle Scholar
  40. [40]
    K. C. Saraswat and F. Mohammadi, Effect of scaling of interconnections on the time delay of VLSI circuits, IEEE J. Solid-State Circuits, vol. SC-17, pp. 275–280 (1982).CrossRefGoogle Scholar
  41. [41]
    E. E. Davidson, Electrical design of a high speed computer packaging system, IEEE Trans. Components, Hybrids, Manuf. Technol., vol. CHMT-6, pp. 272–282 (1983).CrossRefGoogle Scholar
  42. [42]
    E. M. Foster, The electrical effect of single-chip CMOS packages, Proc. 37th IEEE Electronic Components Conf., pp. 342–353 (1987).Google Scholar
  43. [43]
    C.-C. Huang and L. L. Wu, Signal degradation through module pins in VLSI packaging, IBM J. Res. Develop., vol. 31, pp. 489–498 (1987).CrossRefGoogle Scholar
  44. [44]
    R. H. Caverly, Characteristic impedance of integrated circuit wire bonds, IEEE Trans. Microwave Theory and Techniques, vol. MTT-34, pp. 982–984 (1986).CrossRefGoogle Scholar
  45. [45]
    L. W. Schaper and D. I. Amey, Improved electrical performance required for future MOS packaging, IEEE Trans. Comp., Hybr., Manuf. Technol., vol. CHMT-6, pp. 283–289 (1983).CrossRefGoogle Scholar
  46. [46]
    A. J. Rainai, Computing inductive noise of chip packages, AT&T Bell Labs Technical Journal, vol. 63(1), pp. 177–195 (1984).Google Scholar
  47. [47]
    G. A. Katopis, Delta-I noise specification for a high-performance computing machine, Proc. IEEE, vol. 73, pp. 1405–1415 (1985).CrossRefGoogle Scholar
  48. [48]
    R. E. Canright, Jr., A formula to model Delta-I noise, Proc 37th IEEE Electronic Components Conf., pp. 354–364 (1987).Google Scholar
  49. [49]
    Z. A. Syed and A. El Gamal, Single layer routing of power and ground networks in integrated circuits, Journal of Digital Systems, vol. 6, pp. 53–63 (1982).MathSciNetMATHGoogle Scholar
  50. [50]
    H. J. Rothermel and D. A. Mlynski, Computation of power supply nets in VLSI layouts, Proc. 18th Design Automation Conf., pp. 37–42 (1981).Google Scholar
  51. [51]
    C. A. Neugebauer, Comparison of VLSI packaging approaches to wafer scale integration, Proc. IEEE Custom Integrated Circuits Conf., pp. 32–37 (1985).Google Scholar
  52. [52]
    H. Kanai, Low energy LSI and packaging for system performance, IEEE Trans. Comp., Hybr. and Manuf. Technol., vol. CHMT-4, pp. 173–180 (1981).CrossRefGoogle Scholar
  53. [53]
    T. Ikeda, T. Nagano, N. Momma, K. Miyata, H. Higuchi, M. Odaka and K. Ogiue, Advanced BiCMOS technology for high speed VLSI, Digest: IEEE Int. Electron Device Meeting, pp. 408–411 (1986).Google Scholar
  54. [54]
    H. B. Bakoglu and J. D. Meindl, Optimal interconnection circuits for VLSI, IEEE Trans. Electron Devices, vol. ED-32, pp. 903–909 (1985).CrossRefGoogle Scholar
  55. [55]
    K. D. Wagner, A survey of clock distribution techniques in high-speed computer systems, Center for Reliable Computing, Stanford University, CRC Reort No. 86–20 (Dec 1986).Google Scholar
  56. [56]
    S. Abraham and D. D. Gajski, A communication algorithm for a wafer scale integrated multiprocessor, Proc. Int. Conf. Parallel Processing, pp. 147–154 (1984).Google Scholar
  57. [57]
    M. Hatamian and G. Cash, Parallel bit-level pipelined VLSI designs for highspeed signal processing, Proc. IEEE, vol. 75, pp. 1192–1202 (1987).CrossRefGoogle Scholar
  58. [58]
    S.-Y. Kung and R. J. Gal-Ezer, Synchronous vs asynchronous computation in very large scale integrated (VLSI) array processors, Proc. SPIE, vol. 341, pp. 53–65 (1982).Google Scholar
  59. [59]
    D. F. Wann and M. A. Franklin, Asynchronous and clocked control structures for VLSI based interconnection networks, IEEE Trans. Computers, vol. C-32, pp. 284–293 (1983).CrossRefGoogle Scholar
  60. [60]
    R. M. Lea, A WSI image processing module, in Wafer Scale Integration, G. Saucier and J. Trihle (Eds), North-Holland, New York, pp. 43–58 (1986).Google Scholar
  61. [61]
    E. G. Friedman and S. Powell, Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI, IEEE J. Solid-State Circuits, vol. SC-21, pp. 240–246 (1986).CrossRefGoogle Scholar
  62. [62]
    J. Fried, Power and clock distribution for WSI systems, in Wafer Scale Integration, G. Saucier and J. Trilhe (Eds), North-Holland, New York, pp. 127–142 (1986).Google Scholar
  63. [63]
    S. Powell, W. R. Smith and G. Persky, A parasitic extraction program for closely-spaced VLSI interconnects, Proc. IEEE Int. Conf. Computer-Aided Design, pp. 193–195 (1985).Google Scholar
  64. [64]
    E. Friedman, G. Yacoub and S. Powell, A CMOS/SOS VLSI design system, J. Semicustom ICs, vol. 2, pp. 5–11 (1985).Google Scholar
  65. [65]
    M. Shoji, Elimination of process-dependent clock skew in CMOS VLSI, IEEE J. Solid-State Circuits, vol. SC-21, pp. 875–880 (1986).CrossRefGoogle Scholar
  66. [66]
    F. Anceau A synchronous approach for clocking VLSI systems, IEEE J. Solid-State Circuits, vol. SC-17, pp. 51–56 (1982).CrossRefGoogle Scholar
  67. [67]
    C Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, Reading, MA (1980).Google Scholar

Copyright information

© Kluwer Academic Publishers 1989

Authors and Affiliations

  • Stuart K. Tewksbury
    • 1
  1. 1.AT&T Bell LaboratoriesUSA

Personalised recommendations