Proceedings of the International Conference on Information Engineering and Applications (IEA) 2012 pp 337-344 | Cite as
Reliability Analysis of Triple-Redundant CompactPCI SBC
Abstract
Embedded systems based on field-programmable gate arrays (FPGAs) are popularly used in space system. However, as FPGA is especially susceptible to radiation generated by special particles which could lead to soft errors, it is quite important to adopt fault-tolerance technologies to mitigate these problems. In this paper, the research object—a CompactPCI SBC with advanced safety features could realize the functionality of three-redundant systems on a single board. Its complex FPGA-based design technology, which automatically manages the system’s triple-redundant processors and memory, could help dramatically lower software development costs. Reliability assessment technology is introduced to quantitatively evaluate the performance of the CompactPCI SBC. From the hardware architecture and fault tree models of redundancy configurations, probability of failure on demand (PFD) calculation formulas and the corresponding safety integrity level (SIL) for each component unit could be derived.
Keywords
CompactPCI SBC Fault tolerance Reliability analysis Triple redundantReferences
- 1.Andrija V, Marko Č, Borut M (2009) Application of the fault tree analysis for assessment of power system reliability. Reliab Eng Syst Saf 94(6):1116–1127CrossRefGoogle Scholar
- 2.Azambuja JR, Sousa F, Rosa L et al (2009) Evaluating large g rain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs. Proceedings of IEEE international on line testing symposium, vol 24. IEEE Press, Sesimbra-Lisbon, pp 101–106Google Scholar
- 3.Haitao G, Xianhui Y (2007) Simple reliability block diagram method for safety integrity verification. Reliab Eng Syst Saf 92(9):1267–1273CrossRefGoogle Scholar
- 4.International electrotechnical commission (2000) IEC 61508, Functional safety of electrical/electronic/programmable electronic safety-related systems, vol 35, pp 24–26Google Scholar
- 5.Pratt B (2008) TMR with more frequent voting for improved FPGA reliability. Proceeding of the 2008 international conference on engineering of reconfigurable system and algorithms (ERSA) vol 53, pp 153–158Google Scholar
- 6.Pratt B (2008) Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Trans Nucl Sci 55(4):2274–2280MathSciNetCrossRefGoogle Scholar
- 7.Rollins N, Wirth LM, Caffrey M et al (2003) Evaluating TMR techniques in the presence of single event upsets. Proceedings of conference on military and aerospace programmable logic devices (MAPLD), vol 35. Washington, pp 63–63Google Scholar
- 8.William MG (1998) Control systems safety evaluation and reliability, vol 63. ISA, US, pp 14–17Google Scholar
- 9.Zsigmond G, Homolya S, Lendvay M (2009) Application of the continuous -time Markov chains by reliability analysis. SISY 2009-7th international symposium on intelligent systems and informatics, vol 25, pp 69–72Google Scholar