Asynchronous System-on-Chip Interconnect pp 31-40 | Cite as
The Physical (Wire) Layer
Chapter
Abstract
A shared bus is a collection of wires where all interfaces to the wires comply with an ordered protocol devised to avoid deadlocks and data corruption. In the layered bus implementation hierarchy of Figure 4.1 these wires collectively form the lowest layer, the physical layer.
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© John Bainbridge 2002