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Low Power Designs of XOR and XNOR Standard Cells

Conference paper
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Abstract

In this chapter, XOR and XNOR cells are introduced in CMOS standard cell libraries. The XOR and XNOR standard cells are optimized to achieve low-energy delay product (EDP). All circuits are simulated with HSPICE at a SMIC130 nm CMOS technology by a 1.2 V supply voltage. The XOR and XNOR standard cell layouts, abstract design, and standard cell characters are also described.

Keywords

Standard cell XOR and XNOR Abstract Characterization 

Notes

Acknowledgments

This project is supported by Zhejiang Science and Technology Project of China (No. 2010C31116).

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Faculty of Information Science and TechnologyNingbo UniversityNingbo CityChina

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