Low Power Designs of XOR and XNOR Standard Cells
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In this chapter, XOR and XNOR cells are introduced in CMOS standard cell libraries. The XOR and XNOR standard cells are optimized to achieve low-energy delay product (EDP). All circuits are simulated with HSPICE at a SMIC130 nm CMOS technology by a 1.2 V supply voltage. The XOR and XNOR standard cell layouts, abstract design, and standard cell characters are also described.
KeywordsStandard cell XOR and XNOR Abstract Characterization
This project is supported by Zhejiang Science and Technology Project of China (No. 2010C31116).
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