Low Power Designs of XOR and XNOR Standard Cells

Conference paper


In this chapter, XOR and XNOR cells are introduced in CMOS standard cell libraries. The XOR and XNOR standard cells are optimized to achieve low-energy delay product (EDP). All circuits are simulated with HSPICE at a SMIC130 nm CMOS technology by a 1.2 V supply voltage. The XOR and XNOR standard cell layouts, abstract design, and standard cell characters are also described.


Standard cell XOR and XNOR Abstract Characterization 



This project is supported by Zhejiang Science and Technology Project of China (No. 2010C31116).


  1. 1.
    Rabaey, J. M.: Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996Google Scholar
  2. 2.
    Wang, A., Calhoun, B. H., and Chandrakasan, A. P.: Sub-threshold Design for Ultra Low-Power Systems, Springer, pp. 12–102 (2006)Google Scholar
  3. 3.
    Zhuang, N., Wu, H.: A New Design of the CMOS Full Adder, IEEE J. Solid-State Circuits, Vol. 27, No. 5, pp. 840–844 (1992)CrossRefGoogle Scholar
  4. 4.
    Cadence Abstract Generator User Guide, Product Version 5.1.41, July 2007.Google Scholar
  5. 5.
    Liberty™ NCX User Guide Version B-2008.12, December 2008.Google Scholar
  6. 6.
    Synopsys liberty™ User Guide, Volume 1 Version 2003.12, December 2003.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Faculty of Information Science and TechnologyNingbo UniversityNingbo CityChina

Personalised recommendations