Advertisement

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks

  • Ciprian Seiculescu
  • Srinivasan Murali
  • Luca Benini
  • Giovanni De Micheli
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Three-dimensional integrated circuits are a promising approach to push beyond the integration issues and IO bottlenecks of current Systems on Chips (SoCs). Designing the system interconnect for SoCs with many cores is already a challenge for conventional 2D ICs. The degree of freedom offered by the third dimension makes system interconnect design even more complicated and requires a scalable and predictable architecture for the interconnect, in order to achieve design closure. Networks on Chip (NoCs) was presented as a scalable and predictable architecture for system interconnect and therefore is a necessity for 3D integration. Designing an efficient NoC fabric that satisfies performance requirements, but also meets the constraints imposed by 3D technology, is a significant challenge. In this chapter, we move from an overview of communication requirements for current and future SoC platforms, and we analyze through-silicon-via (TSV) vertical interconnection technology, which is emerging as the most promising technology enabler for 3D integration. We then present methodologies and tools for automated 3D interconnect design, focusing on application-specific NoC synthesis for 3D ICs. 3D-NoC synthesis consists of finding the best NoC topology for the application, computing paths for the communication flows, assigning network components on to the layers of the 3D stack, and placing them in each layer. Experiments, performed on several SoC benchmarks demonstrate that 3D-NoCs with application specific tuning bring significant advantages in communication efficiency, power and delay.

Keywords

Power Consumption Silicon Layer Custom Topology Vertical Link Layer Assignment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgment

We would like to acknowledge the financial contribution of CTI under project 10046.2 PFNM-NM and the ARTIST-DESIGN Network of Excellence.

References

  1. 1.
    K. Banerjee et al., “3-D ICs: A Novel Chip Design for Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”, Proc. of the IEEE, vol. 89, no. 5, p. 602, 2001.Google Scholar
  2. 2.
    L. Benini and G. De Micheli, “Networks on Chips: A New SoC Paradigm”, IEEE Computers, vol. 35, no. 1, pp. 70–78, Jan. 2002.Google Scholar
  3. 3.
    E. Beyne, “The Rise of the 3rd Dimension for System Integration”, International Interconnect Technology Conference, pp. 1–5, 2006.Google Scholar
  4. 4.
    B. Goplen and S. Sapatnekar, “Thermal Via Placement in 3D ICs”, Proc. Intl. Symposium on Physical Design, p. 167, 2005.Google Scholar
  5. 5.
    J. Cong et al., “A Thermal-Driven Floorplanning Algorithm for 3D ICs”, ICCAD, Nov. 2004.Google Scholar
  6. 6.
    W.-L. Hung et al., “Interconnect and Thermal-Aware Floorplanning for 3D Microprocessors”, Proc. ISQED, March 2006.Google Scholar
  7. 7.
    S. K. Lim, “Physical Design for 3D System on Package”, IEEE Design & Test of Computers, vol. 22, no. 6, pp. 532–539, 2005.CrossRefGoogle Scholar
  8. 8.
    P. Zhou et al., “3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits”, ICCAD, Nov. 2007.Google Scholar
  9. 9.
    R. Weerasekara et al., “Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs”, ICCAD, 2007.Google Scholar
  10. 10.
    G. H. Loh, Y. Xie, and B. Black. “Processor Design in 3D Die-Stacking Technologies”, IEEE Micro Magazine, vol. 27, no. 3, pp. 31–48, May--June 2007.CrossRefGoogle Scholar
  11. 11.
    I. Loi, F. Angiolini, and L. Benini, “Supporting Vertical Links for 3D Networks on Chip: Toward an Automated Design and Analysis Flow”, Proc. Nanonets, 2007.Google Scholar
  12. 12.
    C. Guedj et al., “Evidence for 3D/2D Transition in Advanced Interconnects”, Proc. IRPS, 2006.Google Scholar
  13. 13.
  14. 14.
  15. 15.
  16. 16.
    N. Miyakawa, “A 3D Prototyping Chip Based on a Wafer-level Stacking Technology”, ASPDAC, 2009.Google Scholar
  17. 17.
    C. Addo-Quaye, “Thermal-Aware Mapping and Placement for 3-D NoC Designs”, Proc. SOCC, 2005.Google Scholar
  18. 18.
    P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet Switched Interconnections”, Proc. DATE, 2000.Google Scholar
  19. 19.
    G. De Micheli and L. Benini, “Networks on Chips: Technology and Tools”, Morgan Kaufmann, San Francisco, CA, First Edition, July 2006.Google Scholar
  20. 20.
    J. Kim et al., “A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3d Architectures”, ISCA, 2007.Google Scholar
  21. 21.
    D. Park et al., “MIRA: A Multi-Layered On-Chip Interconnect Router Architecture”, ISCA, 2008.Google Scholar
  22. 22.
    F. Li et al., “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory”, ISCA, 2006.Google Scholar
  23. 23.
    V. F. Pavlidis and E. G. Friedman, “3-D Topologies for Networks-on-Chip”, IEEE TVLSI, 2007.Google Scholar
  24. 24.
    B. Feero and P. P. Pande, “Performance Evaluation for Three-Dimensional Networks-on-Chip”, Proc. ISVLSI, 2007.Google Scholar
  25. 25.
    J. Hu et al., “System-Level Point-to-Point Communication Synthesis Using Floorplanning Information”, Proc. ASPDAC, 2002.Google Scholar
  26. 26.
    S. Pasricha et al., “Floorplan-Aware Automated Synthesis of Bus-Based Communication Architectures”, Proc. DAC, 2005.Google Scholar
  27. 27.
    S. Murali and G. De Micheli, “An Application-Specific Design Methodology for STbus Crossbar Generation”, Proc. DATE, 2005.Google Scholar
  28. 28.
    S. Murali and G. De Micheli, “SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs”, Proc. DAC, 2004.Google Scholar
  29. 29.
    S. Murali and G. De Micheli, “Bandwidth Constrained Mapping of Cores on to NoC Architectures”, Proc. DATE, 2004.Google Scholar
  30. 30.
    J. Hu and R. Marculescu, “Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures”, Proc. DATE, 2003.Google Scholar
  31. 31.
    S. Murali et al., “Mapping and Physical Planning of Networks on Chip Architectures with Quality-of-Service Guarantees”, Proc. ASPDAC, 2005.Google Scholar
  32. 32.
    A. Pinto et al., “Efficient Synthesis of Networks on Chip”, ICCD 2003, Oct. 2003.Google Scholar
  33. 33.
    W. H. Ho and T. M. Pinkston, “A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns”, HPCA, 2003.Google Scholar
  34. 34.
    T. Ahonen et al., “Topology Optimization for Application Specific Networks on Chip”, Proc. SLIP, 2004.Google Scholar
  35. 35.
    K. Srinivasan et al., “An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks”, ICCAD, 2005.Google Scholar
  36. 36.
    J. Xu et al., “A Design Methodology for Application-Specific Networks-on-Chip”, ACM TECS, 2006.Google Scholar
  37. 37.
    A. Hansson et al., “A Unified Approach to Mapping and Routing on a Combined Guaranteed Service and Best-Effort Network-on-Chip Architectures”, Technical Report No: 2005/00340, Philips Research, Apr. 2005.Google Scholar
  38. 38.
    X. Zhu and S. Malik, “A Hierarchical Modeling Framework for On-Chip Communication Architectures”, ICCD, 2002.Google Scholar
  39. 39.
    S. Murali et al., “Designing Application-Specific Networks on Chips with Floorplan Information”, ICCAD, 2006.Google Scholar
  40. 40.
    S. Murali et al., “Synthesis of Networks on Chips for 3D Systems on Chips”, ASPDAC, 2009.Google Scholar
  41. 41.
    C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, “SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip”, Proc. DATE, 2009.Google Scholar
  42. 42.
    K. Keutzer et al., “System-Level Design: Orthogonalization of Concerns and Platform-Based Design”, IEEE TCAD, 2000.Google Scholar
  43. 43.
    S. Stergiou et al., “´pipesLite: a Synthesis Oriented Design Library for Networks on Chips”, Proc. DATE, 2005.Google Scholar
  44. 44.
    S. N. Adya and I. L. Markov, “Fixed-outline Floorplanning: Enabling Hierarchical Design”, IEEE TVLSI, 2003.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Ciprian Seiculescu
    • 1
  • Srinivasan Murali
  • Luca Benini
  • Giovanni De Micheli
  1. 1.Doctoral-assistent in Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne (EPFL)EPFL IC ISIM LSI1 INF 339 (Bâtiment INF) LausanneSwitzerland

Personalised recommendations