Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

  • Ciprian Seiculescu
  • Srinivasan Murali
  • Luca Benini
  • Giovanni De Micheli


Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores that are not used in an application can be shutdown, while the other islands can still be operational. When one or more of the islands are shutdown, the interconnect should allow the communication between islands that are operational. For this, the NoCs has to be designed efficiently to allow shutdown of VIs, thereby reducing the leakage power consumption. In this chapter, we present methods to design NoC topologies that provide such a support for both 2D and 3D ICs. We show how the concept of VIs need to be considered during topology synthesis phase itself. We also make studies to show the benefits of migrating to 3D-stacked chips for realistic applications that have multiple VIs.


Power Consumption Power Saving Frequency Converter Ground Line Sleep Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



We would like to acknowledge the financial contribution of CTI under project 10046.2 PFNM-NM and the ARTIST-DESIGN Network of Excellence.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Ciprian Seiculescu
    • 1
  • Srinivasan Murali
  • Luca Benini
  • Giovanni De Micheli
  1. 1.LSIEPFLLausanneSwitzerland

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