Adaptive High-Speed Processor Simulation
Instruction set simulators are essential tools in all forms of microprocessor design; simulators play a key role in activities ranging from ASIP design-space exploration to hardware–software co-verification and software development. Simulation speed is the primary concern when functional simulators are used as CPU emulators for software development. Conversely, the ability to measure performance is of critical importance during the exploratory phases of co-design, whereas the ability to use a simulator as a golden reference model is important for hardware–software co-verification. A key challenge is to provide the highest level of performance, for the different observability and performance measuring demands of each use-case. In this chapter, we describe an adaptive simulator designed to meet these diverse requirements. Adaptation takes two forms: first, the simulator has a high-speed JIT compilation capability allowing it to be extended dynamically according to simulated program behavior; and second, it is able to learn how to model the timing behavior of the target processor and thereby deliver approximate performance figures with very low overhead. The simulator maintains a precise model of the architectural state of the processor it simulates, enabling it to be used also as a back-end target for a debugger, to assist in software development, as well as providing a Golden Reference Model to a co-simulation environment. Through the use of these performance-enhancing dynamic adaptations, the simulator is capable of simulating an embedded system at speeds approaching, or even exceeding, real time.
KeywordsTime Slice Basic Block Training Point Cycle Count Strongly Connect Component
- 1.Topham, N., Jones, D.: High speed CPU simulation using JIT binary translation. In: Proceedings of the 4rd Annual Workshop on Modeling, Benchmarking and Simulation: MoBS‘07, (2007).Google Scholar
- 2.Jones, D., Topham, N.: High speed CPU simulation using LTU dynamic binary. In: Proceedings of the HiPEAC Conference. LNCS 5409, Springer, Berlin pp. 50–64, (2009).Google Scholar
- 3.Gao, L., Kraemer, S., Leupers, R., Ascheid, G., Meyr, H.: A fast and generic hybrid simulation approach using c virtual machine. In CASES ’07. ACM (2007).Google Scholar
- 4.Weber, S.J., Moskewicz, M.W., Gries, M., Sauer, C., Keutzer, K.: Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. In Proceedings of CODES+ISSS’04 (2004).Google Scholar
- 5.Snyder, W., Wasson, P., Galbi, D.: Verilator, http://www.veripool.com/verilator.html, (2007).
- 6.ARC International, ARC VTOC Tool, http://www.arc.com/software/simulation/vtoc.html, (2007).
- 7.Powell, D.C., Franke, B.: Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. In CODES+ISSS ’09: Proceedings of the 7th IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis. ACM, New York, NY, pp. 315–324, (2009).Google Scholar
- 8.Franke, B.: Fast cycle-approximate instruction set simulation. In Proceedings of the Workshop on Software and Compilers for Embedded Systems (SCOPES’08) (2008).Google Scholar
- 9.Orr, M.J.: Introduction to radial basis function networks. In Technical Report, Centre for Cognitive Science, University of Edinburgh, (1996).Google Scholar
- 10.Austin, T.M.: Pointer-intensive benchmark suite, http://www.cs.wisc.edu/austin/ptr-dist.html (2007).