Debugging SystemC Platform Models


In the Electronic System Level (ESL) environment, a key factor is the early integration of verification into the design flow. Higher levels of abstraction must not be appealing just for their fast simulation speeds, but also for their flexibility and capabilities when debug and analysis come into play. This creates a demand for new functionalities related to verification in TLM platform models and/or simulation environments. In this chapter, We discuss a mechanism that relies on computational reflection to enable designers to interact with the platform simulation on the fly. This allows them to monitor and change signals or IP internal register values at runtime, so as to explore in high level of details what is happening within each platform module.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Computer Systems Laboratory, Institute of ComputingUniversity of CampinasCampinasBrazil

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