Model-Driven System Validation by Scenarios

  • A. Carioni
  • A. Gargantini
  • E. RiccobeneEmail author
  • P. Scandurra
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 36)


The chapter presents a method for scenario-based validation of embedded system designs provided in terms of UML models. This approach is based on model transformations from SystemC UML graphical models into Abstract State Machine (ASM) formal models, and exploits the scenario-based model validation of the ASMs. This validation approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. A validation tool integrated into an existing model-driven co-design environment to support the proposed scenario-based validation flow is also presented. It allows the designer to functionally validate system components from SystemC UML designs early at high levels of abstraction.


Model-based design System validation Abstract state machines UML 


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Copyright information

© Springer Science+Business Media B.V. 2009

Authors and Affiliations

  • A. Carioni
  • A. Gargantini
  • E. Riccobene
    • 1
    Email author
  • P. Scandurra
  1. 1.Dipartimento di Tecnologie dell’InformazioneUniversità degli Studi di MilanoCremaItaly

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