A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures

  • Giovanni Beltrame
  • Donatella Sciuto
  • Christina Silvano
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 249)

This work introduces an application mapping methodology and case study for multi-processor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is pro- filed, parallelized when possible, then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. After mapping, with the use of hardware objects to handle concurrency, the application power consumption can be further optimized by a task-based scheduler for the remaining software part, without the need for operating system support. The key contributions of this work are: a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption; and a task-based scheduling algorithm that does not require operating system support. The methodology has been applied to the co-exploration of an industrial case study: an MPEG4 VGA real-time encoder.


Design Space Exploration Main Thread Dynamic Voltage Scaling Operating System Support Work Thread 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© International Federation for Information Processin 2008

Authors and Affiliations

  • Giovanni Beltrame
    • 1
  • Donatella Sciuto
    • 1
  • Christina Silvano
    • 1
  1. 1.DEIPolitecnico di MilanoItaly

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