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Reconfigurable Hardware Implementation of the Successive Overrelaxation Method

  • Safaa J. Kasbah
  • Ramzi A. Haraty
  • Issam W. Damaj
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 5)

In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware.We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).

Keywords

Clock Cycle Hardware Implementation General Purpose Processor Successive Overrelaxation Complex Programmable Logic Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Safaa J. Kasbah
    • 1
  • Ramzi A. Haraty
    • 1
  • Issam W. Damaj
  1. 1.Division of Computer Science and MathematicsLebanese American UniversityLebanon

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