Hardware Implementation of the Time-Triggered Ethernet Controller

Conference paper
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)


Hardware Implementation Transmission Delay Message Transmission Host Computer Clock Synchronization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  1. 1.Real-Time Systems GroupVienna University of TechnologyAustria
  2. 2.Real-Time Systems GroupVienna University of TechnologyAustria

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