Verification Model Reduction through Abstractions

Abstract

The major problem still facing researchers in the formal verification of finite state systems is the state space explosion. This problem occurs partly because the domain of each variable of the system model contributes to the global state and verification typically involves an exhaustive search through the state space, to recognize states corresponding to wanted or unwanted system configurations. In telecommunication or hardware systems, most practical problems have a number of states that exceeds the memory capacity of our computers. New techniques of state-space compression, “on-the-fly” computing, combination of various techniques such as so-called partial order methods or symbolic computing with Binary Decision Diagrams (BDDs) have allowed us to tackle problems several orders of magnitude greater. Yet, it is clear that the “brute force” approach to verification is unlikely to ever be sufficient, and we need to develop not only new techniques but also methods to achieve further practical reduction of the state space. Recent research on this topic has shown promising results (e.g. [Loi94]).