A parallel algorithm for minimum cost path computation on polymorphic processor array

  • P. Baglietto
  • M. Maersca
  • M. Migliardi
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh interconnection network. The proposed algorithm has been implemented using the Polymorphic Parallel C language and has been validated through simulation. The proposed algorithm for the Polymorphic Processor Array, delivers the same performance, in terms of computational complexity, as the hypercube interconnection network of the Connection Machine, and as the Gated Connection Network.

Keywords

Interconnection Network Processor Array Minimum Cost Path Destination Vertex Connection Machine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • P. Baglietto
    • 1
  • M. Maersca
    • 2
  • M. Migliardi
    • 1
  1. 1.DIST - University of GenoaGenovaItaly
  2. 2.DEI - University of PaduaPadovaItaly

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